From patchwork Thu May 17 11:19:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilia Lin X-Patchwork-Id: 10406521 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2126A602C2 for ; Thu, 17 May 2018 11:21:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0D40E288D0 for ; Thu, 17 May 2018 11:21:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00D7428A60; Thu, 17 May 2018 11:21:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71EAB288D0 for ; Thu, 17 May 2018 11:21:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752410AbeEQLUs (ORCPT ); Thu, 17 May 2018 07:20:48 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:37614 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752385AbeEQLUn (ORCPT ); Thu, 17 May 2018 07:20:43 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 27C5A60F90; Thu, 17 May 2018 11:20:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1526556042; bh=EvhL1gJN1zWVYRsubZcSWV5nog3teA1yXokZkdUJWFY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ScbbSU3y6hJc12/quaxyZc2JDz5grtlXRlomeSH5+LJvf/0ieAqcPuY7xtb2PeZWK QKRSTbzpteAN+IGf7peTl4kX+7vUzm5f53BgAyYsjmtaK1QwC1pYhR7jAwWATPq6C9 7ATUZqoaS5vwTUZEiquosicLYVjJlYdN2Sukbh6k= Received: from lx-ilial.mea.qualcomm.com (unknown [185.23.60.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilialin@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 091CD60A00; Thu, 17 May 2018 11:20:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1526556040; bh=EvhL1gJN1zWVYRsubZcSWV5nog3teA1yXokZkdUJWFY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hcbrd7RiR3D0qBOozkFavZ6Pu7Wjo3Hy8sJNQ+kn1oktEOgtcTvM2jYgSdglxV8pE wgJs3k2XSaKv2/L6wkLXNgO7J9UTYUlWtH5gfrKMfI1GJp8Tbv2F2wwZh5oHkYJfx6 C8d2NrnOM8ZIJOKjR8itpKYvFGQuUvmHyTVrCuaY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 091CD60A00 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, viresh.kumar@linaro.org, nm@ti.com, lgirdwood@gmail.com, broonie@kernel.org, andy.gross@linaro.org, david.brown@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, rjw@rjwysocki.net, linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, rnayak@codeaurora.org, ilialin@codeaurora.org, amit.kucheria@linaro.org, nicolas.dechesne@linaro.org, celster@codeaurora.org, tfinkel@codeaurora.org Subject: [PATCH v8 13/15] regulator: qcom_spmi: Add support for SAW Date: Thu, 17 May 2018 14:19:13 +0300 Message-Id: <1526555955-29960-14-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526555955-29960-1-git-send-email-ilialin@codeaurora.org> References: <1526555955-29960-1-git-send-email-ilialin@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for SAW controlled regulators. The regulators defined as SAW controlled in the device tree will be controlled through special CPU registers instead of direct SPMI accesses. This is required especially for CPU supply regulators to synchronize with clock scaling and for Automatic Voltage Switching. Signed-off-by: Ilia Lin --- drivers/regulator/qcom_spmi-regulator.c | 133 +++++++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 3 deletions(-) diff --git a/drivers/regulator/qcom_spmi-regulator.c b/drivers/regulator/qcom_spmi-regulator.c index 63c7a0c..9817f1a 100644 --- a/drivers/regulator/qcom_spmi-regulator.c +++ b/drivers/regulator/qcom_spmi-regulator.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include /* Pin control enable input pins. */ #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00 @@ -181,6 +183,23 @@ enum spmi_boost_byp_registers { SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b, }; +enum spmi_saw3_registers { + SAW3_SECURE = 0x00, + SAW3_ID = 0x04, + SAW3_SPM_STS = 0x0C, + SAW3_AVS_STS = 0x10, + SAW3_PMIC_STS = 0x14, + SAW3_RST = 0x18, + SAW3_VCTL = 0x1C, + SAW3_AVS_CTL = 0x20, + SAW3_AVS_LIMIT = 0x24, + SAW3_AVS_DLY = 0x28, + SAW3_AVS_HYSTERESIS = 0x2C, + SAW3_SPM_STS2 = 0x38, + SAW3_SPM_PMIC_DATA_3 = 0x4C, + SAW3_VERSION = 0xFD0, +}; + /* Used for indexing into ctrl_reg. These are offets from 0x40 */ enum spmi_common_control_register_index { SPMI_COMMON_IDX_VOLTAGE_RANGE = 0, @@ -1035,6 +1054,89 @@ static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data) return IRQ_HANDLED; } +#define SAW3_VCTL_DATA_MASK 0xFF +#define SAW3_VCTL_CLEAR_MASK 0x700FF +#define SAW3_AVS_CTL_EN_MASK 0x1 +#define SAW3_AVS_CTL_TGGL_MASK 0x8000000 +#define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00 + +static struct regmap *saw_regmap = NULL; + +static void spmi_saw_set_vdd(void *data) +{ + u32 vctl, data3, avs_ctl, pmic_sts; + bool avs_enabled = false; + unsigned long timeout; + u8 voltage_sel = *(u8 *)data; + + regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl); + regmap_read(saw_regmap, SAW3_VCTL, &vctl); + regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3); + + /* select the band */ + vctl &= ~SAW3_VCTL_CLEAR_MASK; + vctl |= (u32)voltage_sel; + + data3 &= ~SAW3_VCTL_CLEAR_MASK; + data3 |= (u32)voltage_sel; + + /* If AVS is enabled, switch it off during the voltage change */ + avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl; + if (avs_enabled) { + avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK; + regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); + } + + regmap_write(saw_regmap, SAW3_RST, 1); + regmap_write(saw_regmap, SAW3_VCTL, vctl); + regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3); + + timeout = jiffies + usecs_to_jiffies(100); + do { + regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts); + pmic_sts &= SAW3_VCTL_DATA_MASK; + if (pmic_sts == (u32)voltage_sel) + break; + + cpu_relax(); + + } while (time_before(jiffies, timeout)); + + /* After successful voltage change, switch the AVS back on */ + if (avs_enabled) { + pmic_sts &= 0x3f; + avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK; + avs_ctl |= ((pmic_sts - 4) << 10); + avs_ctl |= (pmic_sts << 17); + avs_ctl |= SAW3_AVS_CTL_TGGL_MASK; + regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); + } +} + +static int +spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector) +{ + struct spmi_regulator *vreg = rdev_get_drvdata(rdev); + int ret; + u8 range_sel, voltage_sel; + + ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); + if (ret) + return ret; + + if (0 != range_sel) { + dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \ + range_sel, voltage_sel); + return -EINVAL; + } + + /* Always do the SAW register writes on the first CPU */ + return smp_call_function_single(0, spmi_saw_set_vdd, \ + &voltage_sel, true); +} + +static struct regulator_ops spmi_saw_ops = {}; + static struct regulator_ops spmi_smps_ops = { .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, @@ -1250,6 +1352,7 @@ static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type) } dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV - SPMI_COMMON_REG_DIG_MAJOR_REV]; + if (!force_type) { type = version[SPMI_COMMON_REG_TYPE - SPMI_COMMON_REG_DIG_MAJOR_REV]; @@ -1648,7 +1751,9 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev) struct regmap *regmap; const char *name; struct device *dev = &pdev->dev; - int ret; + struct device_node *node = pdev->dev.of_node; + struct device_node *syscon; + int ret, lenp; struct list_head *vreg_list; vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL); @@ -1665,7 +1770,22 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev) if (!match) return -ENODEV; + if (of_find_property(node, "qcom,saw-reg", &lenp)) { + syscon = of_parse_phandle(node, "qcom,saw-reg", 0); + saw_regmap = syscon_node_to_regmap(syscon); + of_node_put(syscon); + if (IS_ERR(regmap)) + dev_err(dev, "ERROR reading SAW regmap\n"); + } + for (reg = match->data; reg->name; reg++) { + + if (saw_regmap && \ + of_find_property(of_find_node_by_name(node, reg->name), \ + "qcom,saw-slave", &lenp)) { + continue; + } + vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); if (!vreg) return -ENOMEM; @@ -1673,7 +1793,6 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev) vreg->dev = dev; vreg->base = reg->base; vreg->regmap = regmap; - if (reg->ocp) { vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp); if (vreg->ocp_irq < 0) { @@ -1681,7 +1800,6 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev) goto err; } } - vreg->desc.id = -1; vreg->desc.owner = THIS_MODULE; vreg->desc.type = REGULATOR_VOLTAGE; @@ -1698,6 +1816,15 @@ static int qcom_spmi_regulator_probe(struct platform_device *pdev) if (ret) continue; + if (saw_regmap && \ + of_find_property(of_find_node_by_name(node, reg->name), \ + "qcom,saw-leader", &lenp)) { + spmi_saw_ops = *(vreg->desc.ops); + spmi_saw_ops.set_voltage_sel = \ + spmi_regulator_saw_set_voltage; + vreg->desc.ops = &spmi_saw_ops; + } + config.dev = dev; config.driver_data = vreg; config.regmap = regmap;