From patchwork Wed May 23 12:52:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilia Lin X-Patchwork-Id: 10421181 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 31A5A6016C for ; Wed, 23 May 2018 12:54:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2180E28F97 for ; Wed, 23 May 2018 12:54:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1611428F9D; Wed, 23 May 2018 12:54:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8A60E28F97 for ; Wed, 23 May 2018 12:54:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932873AbeEWMyZ (ORCPT ); Wed, 23 May 2018 08:54:25 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56402 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932856AbeEWMxc (ORCPT ); Wed, 23 May 2018 08:53:32 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4734960FB1; Wed, 23 May 2018 12:53:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527080011; bh=/r1w+Yc0St1u/INnDlvOev0yNepaMGc+87aSg5DVMDo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pAz82gc5sDrntYezBFHkcl01ChBSsv2DKxDlOTUXkjIksuibTTgZq/2d7pcSGYDSD t7Zlavvn2oK7ZY8ZQVY4p2Bo948VmcnFwqWVqm7gsqT9BJmzj3ww2lC9zUYSO0FjPd f+3B35pRPhMkBVBJvu+6l22qLI5hNW5TcDxfOMec= Received: from lx-ilial.mea.qualcomm.com (unknown [185.23.60.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilialin@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id A43F660C55; Wed, 23 May 2018 12:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527080009; bh=/r1w+Yc0St1u/INnDlvOev0yNepaMGc+87aSg5DVMDo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LbE4zYO3xcRwrOzrqPRYMAhNvssduQ+9qUJ9T/eXjkm99Pp7dWj4A+K86rNcp5JPb 3NyrFlkktZ02pCMA1nm79ePE8VD6yCNjx5Te1mUGU/JOvpCy1++I3rv+2NnzvNfwA/ U+wWG0BmP4gUgXbl8NqGa337KEjCKFvprK/ijXis= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A43F660C55 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, will.deacon@arm.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, vireshk@kernel.org, ilialin@codeaurora.org, Rajendra Nayak Subject: [PATCH v11 6/8] clk: qcom: cpu-8996: Add support to switch to alternate PLL Date: Wed, 23 May 2018 15:52:59 +0300 Message-Id: <1527079981-11179-7-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org> References: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rajendra Nayak Each of the CPU clusters on msm8996 are powered via a primary PLL and a secondary PLL. The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself, when we temporarily switch to an alternate PLL. Use clock rate change notifiers to support this. Signed-off-by: Rajendra Nayak Signed-off-by: Ilia Lin --- drivers/clk/qcom/clk-cpu-8996.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index d92cad93..620fdc2 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -52,6 +52,7 @@ * detect voltage droops. */ +#include #include #include #include @@ -178,10 +179,14 @@ struct clk_cpu_8996_mux { u32 reg; u8 shift; u8 width; + struct notifier_block nb; struct clk_hw *pll; struct clk_regmap clkr; }; +#define to_clk_cpu_8996_mux_nb(_nb) \ + container_of(_nb, struct clk_cpu_8996_mux, nb) + static inline struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw) { @@ -227,6 +232,26 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) return 0; } +int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret; + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); + + switch (event) { + case PRE_RATE_CHANGE: + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); + break; + case POST_RATE_CHANGE: + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX); + break; + default: + ret = 0; + break; + } + + return notifier_from_errno(ret); +}; const struct clk_ops clk_cpu_8996_mux_ops = { .set_parent = clk_cpu_8996_mux_set_parent, .get_parent = clk_cpu_8996_mux_get_parent, @@ -270,6 +295,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, + .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", .parent_names = (const char *[]){ @@ -289,6 +315,7 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, + .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux", .parent_names = (const char *[]){ @@ -347,6 +374,12 @@ struct clk_regmap *clks[] = { clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); + ret = clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb); + if (ret) + return ret; + + ret = clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb); + return ret; }