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Fri, 25 May 2018 07:51:36 +0000 From: Dong Aisheng To: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, sboyd@kernel.org, mturquette@baylibre.com, shawnguo@kernel.org, Anson.Huang@nxp.com, ping.bai@nxp.com, linux-imx@nxp.com, Dong Aisheng , Stephen Boyd Subject: [PATCH RESEND V4 2/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support Date: Fri, 25 May 2018 15:51:04 +0800 Message-Id: <1527234671-31755-3-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527234671-31755-1-git-send-email-aisheng.dong@nxp.com> References: <1527234671-31755-1-git-send-email-aisheng.dong@nxp.com> MIME-Version: 1.0 X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: HK0P153CA0011.APCP153.PROD.OUTLOOK.COM (2603:1096:203:18::23) To AM0PR04MB4210.eurprd04.prod.outlook.com (2603:10a6:208:66::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(5600026)(48565401081)(4534165)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020); 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This can be used to support frac dividers like below: Divider output clock = Divider input clock x [(frac +1) / (div +1)] where frac/div in register is: 000b - Divide by 1. 001b - Divide by 2. 010b - Divide by 3. Cc: Stephen Boyd Cc: Michael Turquette Signed-off-by: Dong Aisheng --- ChangeLog: v2->v3: * no changes v1->v2: * improve comments suggested by Stephen --- drivers/clk/clk-fractional-divider.c | 10 ++++++++++ include/linux/clk-provider.h | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index fdf625f..7ccde6b 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -40,6 +40,11 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, m = (val & fd->mmask) >> fd->mshift; n = (val & fd->nmask) >> fd->nshift; + if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) { + m++; + n++; + } + if (!n || !m) return parent_rate; @@ -103,6 +108,11 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), &m, &n); + if (fd->flags & CLK_FRAC_DIVIDER_ZERO_BASED) { + m--; + n--; + } + if (fd->lock) spin_lock_irqsave(fd->lock, flags); else diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 3cf522f6..8fad6c8 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -577,6 +577,12 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. + * + * Flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read + * plus one. */ struct clk_fractional_divider { struct clk_hw hw; @@ -596,6 +602,8 @@ struct clk_fractional_divider { #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) + extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags,