diff mbox

[v2,2/2] clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845

Message ID 1530186451-24648-3-git-send-email-tdas@codeaurora.org (mailing list archive)
State Changes Requested, archived
Headers show

Commit Message

Taniya Das June 28, 2018, 11:47 a.m. UTC 
QUPv3 clocks support DFS and thus register the RCGs which require support
for the same.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/gcc-sdm845.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

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Comments

Stephen Boyd July 9, 2018, 6:35 a.m. UTC | #1 
Quoting Taniya Das (2018-06-28 04:47:31)
> @@ -3437,7 +3457,12 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
>         regmap_update_bits(regmap, 0x48190, BIT(0), 0x1);
>         regmap_update_bits(regmap, 0x52004, BIT(22), 0x1);
> 
> -       return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
> +       ret = qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
> +       if (ret)
> +               return ret;
> +
> +       return qcom_cc_register_rcg_dfs(pdev, gcc_dfs_clocks,
> +                                       ARRAY_SIZE(gcc_dfs_clocks));

This looks backwards. We shouldn't expose the clks to drivers and then
make their functionality work by registering dfs clks. The order should
be swapped.

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diff mbox

Patch

diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index e78e6f5..034c762 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3421,9 +3421,29 @@  enum {
 };
 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);

+static struct clk_rcg2 *gcc_dfs_clocks[] = {
+	&gcc_qupv3_wrap0_s0_clk_src,
+	&gcc_qupv3_wrap0_s1_clk_src,
+	&gcc_qupv3_wrap0_s2_clk_src,
+	&gcc_qupv3_wrap0_s3_clk_src,
+	&gcc_qupv3_wrap0_s4_clk_src,
+	&gcc_qupv3_wrap0_s5_clk_src,
+	&gcc_qupv3_wrap0_s6_clk_src,
+	&gcc_qupv3_wrap0_s7_clk_src,
+	&gcc_qupv3_wrap1_s0_clk_src,
+	&gcc_qupv3_wrap1_s1_clk_src,
+	&gcc_qupv3_wrap1_s2_clk_src,
+	&gcc_qupv3_wrap1_s3_clk_src,
+	&gcc_qupv3_wrap1_s4_clk_src,
+	&gcc_qupv3_wrap1_s5_clk_src,
+	&gcc_qupv3_wrap1_s6_clk_src,
+	&gcc_qupv3_wrap1_s7_clk_src,
+};
+
 static int gcc_sdm845_probe(struct platform_device *pdev)
 {
 	struct regmap *regmap;
+	int ret;

 	regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
 	if (IS_ERR(regmap))
@@ -3437,7 +3457,12 @@  static int gcc_sdm845_probe(struct platform_device *pdev)
 	regmap_update_bits(regmap, 0x48190, BIT(0), 0x1);
 	regmap_update_bits(regmap, 0x52004, BIT(22), 0x1);

-	return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
+	if (ret)
+		return ret;
+
+	return qcom_cc_register_rcg_dfs(pdev, gcc_dfs_clocks,
+					ARRAY_SIZE(gcc_dfs_clocks));
 }

 static struct platform_driver gcc_sdm845_driver = {