[3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

Commit Message

Vabhav Sharma Aug. 20, 2018, 6:47 a.m. UTC

From: Yogesh Gaur <[e-mail]>

Add clockgen support for lx2160a.
Added entry for compat 'fsl,lx2160a-clockgen'.
As LX2160A is 16 core, so modified value for NUM_CMUX

Signed-off-by: Tang Yuantian <[e-mail]>
Signed-off-by: Yogesh Gaur <[e-mail]>
Signed-off-by: Vabhav Sharma <[e-mail]>
---
 drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
 drivers/cpufreq/qoriq-cpufreq.c |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

Comments

Stephen Boyd Aug. 28, 2018, 10:39 p.m. UTC | #1

Quoting Vabhav Sharma (2018-08-19 23:47:14)
> From: Yogesh Gaur <[e-mail]>
> 
> Add clockgen support for lx2160a.
> Added entry for compat 'fsl,lx2160a-clockgen'.
> As LX2160A is 16 core, so modified value for NUM_CMUX
> 
> Signed-off-by: Tang Yuantian <[e-mail]>
> Signed-off-by: Yogesh Gaur <[e-mail]>
> Signed-off-by: Vabhav Sharma <[e-mail]>
> ---

Acked-by: Stephen Boyd <[e-mail]>

Crystal Wood Aug. 29, 2018, 12:18 a.m. UTC | #2

On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> From: Yogesh Gaur <[e-mail]>
> 
> Add clockgen support for lx2160a.
> Added entry for compat 'fsl,lx2160a-clockgen'.
> As LX2160A is 16 core, so modified value for NUM_CMUX
> 
> Signed-off-by: Tang Yuantian <[e-mail]>
> Signed-off-by: Yogesh Gaur <[e-mail]>
> Signed-off-by: Vabhav Sharma <[e-mail]>
> ---
>  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
>  drivers/cpufreq/qoriq-cpufreq.c |  1 +
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> index 3a1812f..fc6e308 100644
> --- a/drivers/clk/clk-qoriq.c
> +++ b/drivers/clk/clk-qoriq.c
> @@ -60,7 +60,7 @@ struct clockgen_muxinfo {
>  };
>  
>  #define NUM_HWACCEL	5
> -#define NUM_CMUX	8
> +#define NUM_CMUX	16
>  
>  struct clockgen;
>  
> @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
>  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
>  	},
>  	{
> +		.compat = "fsl,lx2160a-clockgen",
> +		.cmux_groups = {
> +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> +		},
> +		.cmux_to_group = {
> +			0, 0, 0, 0, 1, 1, 1, 1, -1
> +		},
> +		.pll_mask = 0x37,
> +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> +	},

Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8 entries in
cmux_to_group?

-Scott

Vabhav Sharma Aug. 30, 2018, 7:36 a.m. UTC | #3

> -----Original Message-----
> From: [e-mail] <linux-kernel-
> [e-mail]> On Behalf Of Scott Wood
> Sent: Wednesday, August 29, 2018 5:49 AM
> To: Vabhav Sharma <[e-mail]>; linux-
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; linux-arm-
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]
> Cc: Yogesh Narayan Gaur <[e-mail]>; Andy Tang
> <[e-mail]>; Udit Kumar <[e-mail]>;
> [e-mail]; Varun Sethi <[e-mail]>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
> 
> On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > From: Yogesh Gaur <[e-mail]>
> >
> > Add clockgen support for lx2160a.
> > Added entry for compat 'fsl,lx2160a-clockgen'.
> > As LX2160A is 16 core, so modified value for NUM_CMUX
> >
> > Signed-off-by: Tang Yuantian <[e-mail]>
> > Signed-off-by: Yogesh Gaur <[e-mail]>
> > Signed-off-by: Vabhav Sharma <[e-mail]>
> > ---
> >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> >  2 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > 3a1812f..fc6e308 100644
> > --- a/drivers/clk/clk-qoriq.c
> > +++ b/drivers/clk/clk-qoriq.c
> > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> >
> >  #define NUM_HWACCEL	5
> > -#define NUM_CMUX	8
> > +#define NUM_CMUX	16
> >
> >  struct clockgen;
> >
> > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
> >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> >  	},
> >  	{
> > +		.compat = "fsl,lx2160a-clockgen",
> > +		.cmux_groups = {
> > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > +		},
> > +		.cmux_to_group = {
> > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > +		},
> > +		.pll_mask = 0x37,
> > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > +	},
> 
> Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> entries in cmux_to_group?
Configuration is 16 cores,8 cluster with 2 cores in each cluster
> 
> -Scott

Crystal Wood Aug. 30, 2018, 5:39 p.m. UTC | #4

On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > -----Original Message-----
> > From: [e-mail] <linux-kernel-
> > [e-mail]> On Behalf Of Scott Wood
> > Sent: Wednesday, August 29, 2018 5:49 AM
> > To: Vabhav Sharma <[e-mail]>; linux-
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; linux-arm-
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail]
> > Cc: Yogesh Narayan Gaur <[e-mail]>; Andy Tang
> > <[e-mail]>; Udit Kumar <[e-mail]>;
> > [e-mail]; Varun Sethi <[e-mail]>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> > 
> > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > From: Yogesh Gaur <[e-mail]>
> > > 
> > > Add clockgen support for lx2160a.
> > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > 
> > > Signed-off-by: Tang Yuantian <[e-mail]>
> > > Signed-off-by: Yogesh Gaur <[e-mail]>
> > > Signed-off-by: Vabhav Sharma <[e-mail]>
> > > ---
> > >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> > >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> > >  2 files changed, 14 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > > 3a1812f..fc6e308 100644
> > > --- a/drivers/clk/clk-qoriq.c
> > > +++ b/drivers/clk/clk-qoriq.c
> > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> > > 
> > >  #define NUM_HWACCEL	5
> > > -#define NUM_CMUX	8
> > > +#define NUM_CMUX	16
> > > 
> > >  struct clockgen;
> > > 
> > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] =
> > > {
> > >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > >  	},
> > >  	{
> > > +		.compat = "fsl,lx2160a-clockgen",
> > > +		.cmux_groups = {
> > > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > +		},
> > > +		.cmux_to_group = {
> > > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > > +		},
> > > +		.pll_mask = 0x37,
> > > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > +	},
> > 
> > Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> > entries in cmux_to_group?
> 
> Configuration is 16 cores,8 cluster with 2 cores in each cluster

So?  This is about cmuxes, not cores.  You're increasing the array without
ever using the new size.

-Scott

Crystal Wood Aug. 30, 2018, 5:42 p.m. UTC | #5

On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > -----Original Message-----
> > > From: [e-mail] <linux-kernel-
> > > [e-mail]> On Behalf Of Scott Wood
> > > Sent: Wednesday, August 29, 2018 5:49 AM
> > > To: Vabhav Sharma <[e-mail]>; linux-
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; linux-arm-
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]
> > > Cc: Yogesh Narayan Gaur <[e-mail]>; Andy Tang
> > > <[e-mail]>; Udit Kumar <[e-mail]>;
> > > [e-mail]; Varun Sethi <[e-mail]>
> > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > > lx2160a
> > > 
> > > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > > From: Yogesh Gaur <[e-mail]>
> > > > 
> > > > Add clockgen support for lx2160a.
> > > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > > 
> > > > Signed-off-by: Tang Yuantian <[e-mail]>
> > > > Signed-off-by: Yogesh Gaur <[e-mail]>
> > > > Signed-off-by: Vabhav Sharma <[e-mail]>
> > > > ---
> > > >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> > > >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> > > >  2 files changed, 14 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > > > 3a1812f..fc6e308 100644
> > > > --- a/drivers/clk/clk-qoriq.c
> > > > +++ b/drivers/clk/clk-qoriq.c
> > > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> > > > 
> > > >  #define NUM_HWACCEL	5
> > > > -#define NUM_CMUX	8
> > > > +#define NUM_CMUX	16
> > > > 
> > > >  struct clockgen;
> > > > 
> > > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[]
> > > > =
> > > > {
> > > >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > >  	},
> > > >  	{
> > > > +		.compat = "fsl,lx2160a-clockgen",
> > > > +		.cmux_groups = {
> > > > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > > +		},
> > > > +		.cmux_to_group = {
> > > > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > > > +		},
> > > > +		.pll_mask = 0x37,
> > > > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > +	},
> > > 
> > > Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> > > entries in cmux_to_group?
> > 
> > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> 
> So?  This is about cmuxes, not cores.  You're increasing the array without
> ever using the new size.

Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator, because
the array was of length 8.  Probably the array should be changed to NUM_CMUX+1
so every array can be -1 terminated.

-Scott

Andy Tang Aug. 31, 2018, 6:12 a.m. UTC | #6

Hi Scott,

Please see my replay inline.

> -----Original Message-----
> From: linux-arm-kernel <[e-mail]>
> On Behalf Of Scott Wood
> Sent: 2018年8月31日 1:43
> To: Vabhav Sharma <[e-mail]>;
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]
> Cc: Yogesh Narayan Gaur <[e-mail]>; Andy Tang
> <[e-mail]>; [e-mail]; Varun Sethi
> <[e-mail]>; Udit Kumar <[e-mail]>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> lx2160a
> 
> On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > > -----Original Message-----
> > > > From: [e-mail] <linux-kernel-
> > > > [e-mail]> On Behalf Of Scott Wood
> > > > Sent: Wednesday, August 29, 2018 5:49 AM
> > > > To: Vabhav Sharma <[e-mail]>; linux-
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; linux-arm-
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail];
> > > > [e-mail]; [e-mail]
> > > > Cc: Yogesh Narayan Gaur <[e-mail]>; Andy
> Tang
> > > > <[e-mail]>; Udit Kumar <[e-mail]>;
> > > > [e-mail]; Varun Sethi <[e-mail]>
> > > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support
> > > > for lx2160a
> > > >
> > > > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > > > From: Yogesh Gaur <[e-mail]>
> > > > >
> > > > > Add clockgen support for lx2160a.
> > > > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > > >
> > > > > Signed-off-by: Tang Yuantian <[e-mail]>
> > > > > Signed-off-by: Yogesh Gaur <[e-mail]>
> > > > > Signed-off-by: Vabhav Sharma <[e-mail]>
> > > > > ---
> > > > >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> > > > >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> > > > >  2 files changed, 14 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> > > > > index
> > > > > 3a1812f..fc6e308 100644
> > > > > --- a/drivers/clk/clk-qoriq.c
> > > > > +++ b/drivers/clk/clk-qoriq.c
> > > > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> > > > >
> > > > >  #define NUM_HWACCEL	5
> > > > > -#define NUM_CMUX	8
> > > > > +#define NUM_CMUX	16
> > > > >
> > > > >  struct clockgen;
> > > > >
> > > > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo
> > > > > chipinfo[] = {
> > > > >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > >  	},
> > > > >  	{
> > > > > +		.compat = "fsl,lx2160a-clockgen",
> > > > > +		.cmux_groups = {
> > > > > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > > > +		},
> > > > > +		.cmux_to_group = {
> > > > > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > > > > +		},
> > > > > +		.pll_mask = 0x37,
> > > > > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > > +	},
> > > >
> > > > Why are you increasing NUM_CMUX beyond 8 for a chip that only
> has
> > > > 8 entries in cmux_to_group?
> > >
> > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> >
> > So?  This is about cmuxes, not cores.  You're increasing the array
> > without ever using the new size.
> 
> Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator,
> because the array was of length 8.  Probably the array should be changed
> to NUM_CMUX+1 so every array can be -1 terminated.
> 
[Andy] How about we add -1 terminator to p4080 and increase NUM_CMUX to 16?
We don't want to increase NUM_CMUX each time new soc with more cmuxes added.

BR,
Andy Tang

> -Scott
> 
> 
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Crystal Wood Aug. 31, 2018, 8:28 p.m. UTC | #7

On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> Hi Scott,
> 
> Please see my replay inline.
> 
> > -----Original Message-----
> > From: linux-arm-kernel <[e-mail]>
> > On Behalf Of Scott Wood
> > Sent: 2018年8月31日 1:43
> > To: Vabhav Sharma <[e-mail]>;
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail]
> > Cc: Yogesh Narayan Gaur <[e-mail]>; Andy Tang
> > <[e-mail]>; [e-mail]; Varun Sethi
> > <[e-mail]>; Udit Kumar <[e-mail]>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> > 
> > On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > > On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > > > 
> > > > > Why are you increasing NUM_CMUX beyond 8 for a chip that only
> > 
> > has
> > > > > 8 entries in cmux_to_group?
> > > > 
> > > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> > > 
> > > So?  This is about cmuxes, not cores.  You're increasing the array
> > > without ever using the new size.
> > 
> > Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator,
> > because the array was of length 8.  Probably the array should be changed
> > to NUM_CMUX+1 so every array can be -1 terminated.
> > 
> 
> [Andy] How about we add -1 terminator to p4080 and increase NUM_CMUX to 16?

Why 16?  What does such a change have to do with this chip, which according to
the rest of the patch has 8 cmuxes?

> We don't want to increase NUM_CMUX each time new soc with more cmuxes added.

You don't want to have to make a trivial change each time you exceed a limit
that has yet to be exceeded once since NUM_CMUX was added?  This isn't ABI or
in any other way hard to change.  It's right in the same file as the chip
description you'd be adding.

And even if a chip did come along with 16 cmuxes, you'd then need to increase
the array to 17 to hold the -1 if you don't want to leave a situation like the
p4080 is in now, where a chip's cmux array could be broken by increasing
NUM_CMUX further.

-Scott

Andy Tang Sept. 3, 2018, 1:17 a.m. UTC | #8

Hi Scott,

Please see my replay in line.

> -----Original Message-----
> From: Linuxppc-dev
> <linuxppc-dev-bounces+b29983=[e-mail]> On
> Behalf Of Scott Wood
> Sent: 2018年9月1日 4:29
> To: Andy Tang <[e-mail]>; Vabhav Sharma
> <[e-mail]>; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]
> Cc: Yogesh Narayan Gaur <[e-mail]>;
> [e-mail]; Udit Kumar <[e-mail]>; Varun Sethi
> <[e-mail]>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> lx2160a
> 
> On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> > Hi Scott,
> >
> > Please see my replay inline.
> >
> > > -----Original Message-----
> > > From: linux-arm-kernel
> > > <[e-mail]>
> > > On Behalf Of Scott Wood
> > > Sent: 2018年8月31日 1:43
> > > To: Vabhav Sharma <[e-mail]>;
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]
> > > Cc: Yogesh Narayan Gaur <[e-mail]>; Andy Tang
> > > <[e-mail]>; [e-mail]; Varun Sethi
> > > <[e-mail]>; Udit Kumar <[e-mail]>
> > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support
> > > for lx2160a
> > >
> > > On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > > > On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > > > >
> > > > > > Why are you increasing NUM_CMUX beyond 8 for a chip that
> only
> > >
> > > has
> > > > > > 8 entries in cmux_to_group?
> > > > >
> > > > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> > > >
> > > > So?  This is about cmuxes, not cores.  You're increasing the array
> > > > without ever using the new size.
> > >
> > > Oh, and you also broke p4080 which has 8 cmuxes but no -1
> > > terminator, because the array was of length 8.  Probably the array
> > > should be changed to NUM_CMUX+1 so every array can be -1
> terminated.
> > >
> >
> > [Andy] How about we add -1 terminator to p4080 and increase
> NUM_CMUX to 16?
> 
> Why 16?  What does such a change have to do with this chip, which
> according to the rest of the patch has 8 cmuxes?
[Andy] NUM_CMUX is a limitation number. We better give it an extra buffer, not exactly equal to the limitation.
16 is the limitation number with extra buffer.

> 
> > We don't want to increase NUM_CMUX each time new soc with more
> cmuxes added.
> 
> You don't want to have to make a trivial change each time you exceed a
> limit that has yet to be exceeded once since NUM_CMUX was added?
> This isn't ABI or in any other way hard to change.  It's right in the same file
> as the chip description you'd be adding.
> 
> And even if a chip did come along with 16 cmuxes, you'd then need to
> increase the array to 17 to hold the -1 if you don't want to leave a situation
> like the
> p4080 is in now, where a chip's cmux array could be broken by increasing
> NUM_CMUX further.
> 
[Andy] Adding buffer to a limitation number is always a good habit when coding. We often forget to increase this value when
a new chip with more cmuxes added. Like this patch, we didn't increase this value at first. We spent a lot of time finding out that NUM_CMUX needs to be increased too.
It is a personal preference how to set this value. I think it is better to increase it to 16, not NUM_CMUX+1 as long as we fix the P4080 issue
even though it is a trivial change. And I agree the description needs to be updated.

BR,
Andy

> -Scott

Crystal Wood Sept. 3, 2018, 8:33 p.m. UTC | #9

On Mon, 2018-09-03 at 01:17 +0000, Andy Tang wrote:
> Hi Scott,
> 
> Please see my replay in line.
> 
> > -----Original Message-----
> > From: Linuxppc-dev
> > <linuxppc-dev-bounces+b29983=[e-mail]> On
> > Behalf Of Scott Wood
> > Sent: 2018年9月1日 4:29
> > To: Andy Tang <[e-mail]>; Vabhav Sharma
> > <[e-mail]>; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail];
> > [e-mail]; [e-mail]; [e-mail];
> > [e-mail]; [e-mail]
> > Cc: Yogesh Narayan Gaur <[e-mail]>;
> > [e-mail]; Udit Kumar <[e-mail]>; Varun Sethi
> > <[e-mail]>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> > 
> > On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> > > We don't want to increase NUM_CMUX each time new soc with more
> > 
> > cmuxes added.
> > 
> > You don't want to have to make a trivial change each time you exceed a
> > limit that has yet to be exceeded once since NUM_CMUX was added?
> > This isn't ABI or in any other way hard to change.  It's right in the same
> > file
> > as the chip description you'd be adding.
> > 
> > And even if a chip did come along with 16 cmuxes, you'd then need to
> > increase the array to 17 to hold the -1 if you don't want to leave a
> > situation
> > like the
> > p4080 is in now, where a chip's cmux array could be broken by increasing
> > NUM_CMUX further.
> > 
> 
> [Andy] Adding buffer to a limitation number is always a good habit when
> coding. We often forget to increase this value when
> a new chip with more cmuxes added. 

"often"?  There has never been a new chip added with more cmuxes than p4080's
8, and if one does come along and you forget, the compiler should complain
about exceeding the array length with a static initializer.  This isn't like
an array that is filled with a runtime-determined length.

> Like this patch, we didn't increase this value at first. We spent a lot of
> time finding out that NUM_CMUX needs to be increased too.

Are you talking about some other chip that you haven't sent a patch for yet? 
Or is the cmux array for this chip wrong?  What specifically did you see
happen "at first"?

> It is a personal preference how to set this value. I think it is better to
> increase it to 16, not NUM_CMUX+1 as long as we fix the P4080 issue
> even though it is a trivial change. And I agree the description needs to be
> updated.

I'm not the clock maintainer, so it's not up to me, but I don't see the point
in setting it to an arbitrary number, and I do not agree that increasing
NUM_CMUX is a suitable replacement for NUM_CMUX+1 in cmux_to_group[], as that
array should be one larger than cmux[] in order to allow every chip to have a
-1 terminator.  In any case, any change to NUM_CMUX should be a separate patch
because it's not required for lx2160a support (assuming lx2160a was correctly
described by this patch).

-Scott

Andy Tang Sept. 4, 2018, 3:08 a.m. UTC | #10

Hi Scott,

Please see my replay inline.

> -----Original Message-----
> From: linux-arm-kernel <[e-mail]>
> On Behalf Of Scott Wood
> Sent: 2018年9月4日 4:34
> To: Andy Tang <[e-mail]>; Vabhav Sharma
> <[e-mail]>; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail];
> [e-mail]; [e-mail]; [e-mail];
> [e-mail]; [e-mail]
> Cc: Yogesh Narayan Gaur <[e-mail]>;
> [e-mail]; Varun Sethi <[e-mail]>; Udit Kumar
> <[e-mail]>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> lx2160a
> 
> On Mon, 2018-09-03 at 01:17 +0000, Andy Tang wrote:
> > Hi Scott,
> >
> > Please see my replay in line.
> >
> > > -----Original Message-----
> > > From: Linuxppc-dev
> > > <linuxppc-dev-bounces+b29983=[e-mail]> On
> > > Behalf Of Scott Wood
> > > Sent: 2018年9月1日 4:29
> > > To: Andy Tang <[e-mail]>; Vabhav Sharma
> > > <[e-mail]>; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]; [e-mail];
> > > [e-mail]; [e-mail]
> > > Cc: Yogesh Narayan Gaur <[e-mail]>;
> > > [e-mail]; Udit Kumar <[e-mail]>; Varun
> Sethi
> > > <[e-mail]>
> > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support
> > > for lx2160a
> > >
> > > On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> > > > We don't want to increase NUM_CMUX each time new soc with
> more
> > >
> > > cmuxes added.
> > >
> > > You don't want to have to make a trivial change each time you exceed
> > > a limit that has yet to be exceeded once since NUM_CMUX was added?
> > > This isn't ABI or in any other way hard to change.  It's right in
> > > the same file as the chip description you'd be adding.
> > >
> > > And even if a chip did come along with 16 cmuxes, you'd then need to
> > > increase the array to 17 to hold the -1 if you don't want to leave a
> > > situation like the
> > > p4080 is in now, where a chip's cmux array could be broken by
> > > increasing NUM_CMUX further.
> > >
> >
> > [Andy] Adding buffer to a limitation number is always a good habit
> > when coding. We often forget to increase this value when a new chip
> > with more cmuxes added.
> 
> "often"?  There has never been a new chip added with more cmuxes
> than p4080's 8, and if one does come along and you forget, the compiler
> should complain about exceeding the array length with a static initializer.
> This isn't like an array that is filled with a runtime-determined length.
> 
> > Like this patch, we didn't increase this value at first. We spent a
> > lot of time finding out that NUM_CMUX needs to be increased too.
> 
> Are you talking about some other chip that you haven't sent a patch for
> yet?
> Or is the cmux array for this chip wrong?  What specifically did you see
> happen "at first"?
> 
[Andy] Sorry, "Often" is not a right word. I meant we tend to add new soc without updating NUM_CMUX.
 
> > It is a personal preference how to set this value. I think it is
> > better to increase it to 16, not NUM_CMUX+1 as long as we fix the
> > P4080 issue even though it is a trivial change. And I agree the
> > description needs to be updated.
> 
> I'm not the clock maintainer, so it's not up to me, but I don't see the point
> in setting it to an arbitrary number, and I do not agree that increasing
> NUM_CMUX is a suitable replacement for NUM_CMUX+1 in
> cmux_to_group[], as that array should be one larger than cmux[] in order
> to allow every chip to have a
> -1 terminator.  In any case, any change to NUM_CMUX should be a
> separate patch because it's not required for lx2160a support (assuming
> lx2160a was correctly described by this patch).
[Andy] I don't see any impropriate about your suggestion. so we are going to do in your way.

Thanks,
Andy
> 
> -Scott
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
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> s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=02
> %7C01%7Candy.tang%40nxp.com%7Cdbc824fc39674711316208d611dcf
> 61b%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63671603
> 8060797113&amp;sdata=iCLKGMEzRX2dpH5%2Bf4NWIiPDc5L5NpTcpZ7X
> usehdIw%3D&amp;reserved=0

Patch

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..fc6e308 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -60,7 +60,7 @@  struct clockgen_muxinfo {
 };
 
 #define NUM_HWACCEL	5
-#define NUM_CMUX	8
+#define NUM_CMUX	16
 
 struct clockgen;
 
@@ -570,6 +570,17 @@  static const struct clockgen_chipinfo chipinfo[] = {
 		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
 	},
 	{
+		.compat = "fsl,lx2160a-clockgen",
+		.cmux_groups = {
+			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+		},
+		.cmux_to_group = {
+			0, 0, 0, 0, 1, 1, 1, 1, -1
+		},
+		.pll_mask = 0x37,
+		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
+	},
+	{
 		.compat = "fsl,p2041-clockgen",
 		.guts_compat = "fsl,qoriq-device-config-1.0",
 		.init_periph = p2041_init_periph,
@@ -1424,6 +1435,7 @@  CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
 
 /* Legacy nodes */
 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 3d773f6..83921b7 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -295,6 +295,7 @@  static const struct of_device_id node_matches[] __initconst = {
 	{ .compatible = "fsl,ls1046a-clockgen", },
 	{ .compatible = "fsl,ls1088a-clockgen", },
 	{ .compatible = "fsl,ls2080a-clockgen", },
+	{ .compatible = "fsl,lx2160a-clockgen", },
 	{ .compatible = "fsl,p4080-clockgen", },
 	{ .compatible = "fsl,qoriq-clockgen-1.0", },
 	{ .compatible = "fsl,qoriq-clockgen-2.0", },