From patchwork Fri Sep 14 21:48:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10601259 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 55E3814BD for ; Fri, 14 Sep 2018 21:57:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C1752BCD9 for ; Fri, 14 Sep 2018 21:57:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3001E2BCE5; Fri, 14 Sep 2018 21:57:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7CACE2BCE2 for ; Fri, 14 Sep 2018 21:57:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728295AbeIODNe (ORCPT ); Fri, 14 Sep 2018 23:13:34 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10971 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726942AbeIODNe (ORCPT ); Fri, 14 Sep 2018 23:13:34 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 14:57:16 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 14:57:13 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 14:57:13 -0700 Received: from tbergstrom-lnx.Nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Sep 2018 21:57:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id DFB7BF83717; Sat, 15 Sep 2018 00:48:17 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 04/14] clk: tegra: emc: prepare for Tegra210 parent table Date: Sat, 15 Sep 2018 00:48:05 +0300 Message-ID: <1536961695-27809-5-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> References: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL108.nvidia.com (172.18.146.13) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536962236; bh=MHlXaLY90wRY7+nsKavrcE02Ke0EdcDlCmdM6oAEwSQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type:X-Originating-IP:X-ClientProxiedBy; b=sB18ilfaZTcqzjgFe0P+jNFngQojCWw4Dx8yAusLQcEBcYbzcuGfzxFR36pe75hkh eam2ndVHcaJpbH382pedRrxvRTyN9tIDqZokiREAC6my9clQpiW1Oo53wb+YrjWpVY ixR9rgwMtZ0znDGi/ek+CDR8evSo6LyKP++dyCPZbDd3KVb1KQtKEZa0EX8EV1l3+v GzrZxVHr4+ZcxEr7Te12T/5bmmB6B07dAK6HQz1zHDxYRpzh5St8S2fCR7To+BUBU0 WUc5kBII73Jw+0c6+3IJ+8m3ydpbr6ZwxoaUuE60Iz2O4sFHSac/h+VG5k0SPzfkIo WYhgm1xZMLLmg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The set of possible emc parents is different in Tegra124 compared to Tegra210. Hence make this list a Tegra124 specific table and adjust the users to allow for other tables. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-emc.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk-emc.c b/drivers/clk/tegra/clk-emc.c index e836a9b..84fa806 100644 --- a/drivers/clk/tegra/clk-emc.c +++ b/drivers/clk/tegra/clk-emc.c @@ -44,7 +44,7 @@ #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \ CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT) -static const char * const emc_parent_clk_names[] = { +static const char * const tegra124_emc_parent_clk_names[] = { "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", "pll_c_ud" }; @@ -376,7 +376,9 @@ static int emc_set_rate(struct clk_hw *hw, unsigned long rate, static int load_one_timing_from_dt(struct tegra_clk_emc *tegra, struct emc_timing *timing, - struct device_node *node) + struct device_node *node, + const * char const *parent_names, + int num_parents) { int err, i; u32 tmp; @@ -404,9 +406,9 @@ static int load_one_timing_from_dt(struct tegra_clk_emc *tegra, } timing->parent_index = 0xff; - for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) { - if (!strcmp(emc_parent_clk_names[i], - __clk_get_name(timing->parent))) { + for (i = 0; i < num_parents; i++) { + if (!strcmp(parent_names([i], + __clk_get_name(timing->parent)))) { timing->parent_index = i; break; } @@ -436,7 +438,9 @@ static int cmp_timings(const void *_a, const void *_b) static int load_timings_from_dt(struct tegra_clk_emc *tegra, struct device_node *node, - u32 ram_code) + u32 ram_code, + const * char const *parent_names, + int num_parents) { struct device_node *child; int child_count = of_get_child_count(node); @@ -452,7 +456,8 @@ static int load_timings_from_dt(struct tegra_clk_emc *tegra, for_each_child_of_node(node, child) { struct emc_timing *timing = tegra->timings + (i++); - err = load_one_timing_from_dt(tegra, timing, child); + err = load_one_timing_from_dt(tegra, timing, child, + parent_names, num_parents); if (err) { of_node_put(child); return err; @@ -503,7 +508,9 @@ struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, * Store timings for all ram codes as we cannot read the * fuses until the apbmisc driver is loaded. */ - err = load_timings_from_dt(tegra, node, node_ram_code); + err = load_timings_from_dt(tegra, node, node_ram_code, + tegra124_emc_parents, + ARRAY_SIZE(tegra124_emc_parents)); of_node_put(node); if (err) return ERR_PTR(err);