From patchwork Fri Sep 14 21:48:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 10601271 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 56E24933 for ; Fri, 14 Sep 2018 22:27:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A8DE2BAF9 for ; Fri, 14 Sep 2018 22:27:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E67B2BB20; Fri, 14 Sep 2018 22:27:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4AF62BAF9 for ; Fri, 14 Sep 2018 22:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726969AbeIODnk (ORCPT ); Fri, 14 Sep 2018 23:43:40 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12737 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728031AbeIODnk (ORCPT ); Fri, 14 Sep 2018 23:43:40 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 15:27:17 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 15:27:13 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 15:27:13 -0700 Received: from tbergstrom-lnx.Nvidia.com (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Sep 2018 22:27:12 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 1A907F83745; Sat, 15 Sep 2018 00:48:18 +0300 (EEST) From: Peter De Schrijver To: CC: Peter De Schrijver Subject: [RFC 08/14] clk: tegra: clock changes for emc scaling Date: Sat, 15 Sep 2018 00:48:09 +0300 Message-ID: <1536961695-27809-9-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> References: <1536961695-27809-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536964037; bh=H1mp48+VLEDxpFbo8poDkQ0Kmvdpiad/OZoXzHyAk7g=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type:X-Originating-IP:X-ClientProxiedBy; b=Pqje4mqhKje43RmDxut5qbQnW5xrn19LU/8189ybN0Xf9NJHJOdcj0hSmiSbR24/g RL/LADpA1Ye2/OLgMPu45uHLJ5Pu30K6nPWSOEOhdNmQZ2Mu9XwVkFAKYjWGlIBmDU 3tsvosF6YmrZbDnovrKSpjSzBqGuw9q0mwbP/hsmGaM56bcHXksUroURnH969mneAQ Dx8TFU2HuFzXSxDJf3bKRUkSXuKvLPLYQ5kPRnNlAoLAjQ1KCc1X05Kwv2Tpsv5S7X Ebd2QuJhxmsJz2UNY/MJhit42T6xARvm2QaZkuy4KGMw/CXd4AZD2nE+OA3mYXiXU7 EnC0Qroy2atgw== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP 1) Introduce low jitter paths for pllp and pll_mb used by the EMC scaling code 2) Remove the old emc_mux clock and don't use the common EMC clock definition. This will be replaced by a new clock defined in the EMC scaling code 3) Export functions to allow accessing the CAR register required for EMC clock scaling. This function will be used to access the CAR register as part of the scaling sequence. The scaling sequence may also need to be run when the DRAM temperature crosses a certain limit. To avoid deadlocks it's easier to keep the whole sequence in one place. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra210.c | 53 ++++++++++++++++++++++++++------ include/dt-bindings/clock/tegra210-car.h | 2 ++ 2 files changed, 46 insertions(+), 9 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 72de0e9..6286b1a 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2368,7 +2368,7 @@ struct utmi_clk_param { [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true }, [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true }, [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true }, - [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true }, + [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = false }, [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true }, [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true }, [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true }, @@ -2780,6 +2780,34 @@ void tegra210_put_utmipll_out_iddq(void) } EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq); +void tegra210_clk_emc_update_setting(u32 emc_src_value) +{ + unsigned long flags = 0; + + spin_lock_irqsave(&emc_lock, flags); + + writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC); + readl(clk_base + CLK_SOURCE_EMC); + + spin_unlock_irqrestore(&emc_lock, flags); +} +EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting); + +u32 tegra210_clk_emc_get_setting(void) +{ + unsigned long flags = 0; + u32 val; + + spin_lock_irqsave(&emc_lock, flags); + + val = readl_relaxed(clk_base + CLK_SOURCE_EMC); + + spin_unlock_irqrestore(&emc_lock, flags); + + return val; +} +EXPORT_SYMBOL_GPL(tegra210_clk_emc_get_setting); + static void tegra210_utmi_param_configure(void) { u32 reg; @@ -3016,13 +3044,8 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, CLK_SOURCE_LA, 0); - /* emc mux */ - clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, - ARRAY_SIZE(mux_pllmcp_clkm), 0, - clk_base + CLK_SOURCE_EMC, - 29, 3, 0, &emc_lock); - clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, + clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, &emc_lock); clks[TEGRA210_CLK_MC] = clk; @@ -3088,13 +3111,13 @@ static void __init tegra210_pll_init(void __iomem *clk_base, /* PLLM */ clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, - CLK_SET_RATE_GATE, &pll_m_params, NULL); + CLK_IS_CRITICAL | CLK_SET_RATE_GATE, &pll_m_params, NULL); clk_register_clkdev(clk, "pll_m", NULL); clks[TEGRA210_CLK_PLL_M] = clk; /* PLLMB */ clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, - CLK_SET_RATE_GATE, &pll_mb_params, NULL); + CLK_IS_CRITICAL | CLK_SET_RATE_GATE, &pll_mb_params, NULL); clk_register_clkdev(clk, "pll_mb", NULL); clks[TEGRA210_CLK_PLL_MB] = clk; @@ -3104,6 +3127,18 @@ static void __init tegra210_pll_init(void __iomem *clk_base, clk_register_clkdev(clk, "pll_m_ud", NULL); clks[TEGRA210_CLK_PLL_M_UD] = clk; + /* PLLMB_UD */ + clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb", + CLK_SET_RATE_PARENT, 1, 1); + clk_register_clkdev(clk, "pll_mb_ud", NULL); + clks[TEGRA210_CLK_PLL_MB_UD] = clk; + + /* PLLP_UD */ + clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p", + 0, 1, 1); + clks[TEGRA210_CLK_PLL_P_UD] = clk; + + /* PLLU_VCO */ if (!tegra210_init_pllu()) { clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 5df857a..453f814 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -396,6 +396,8 @@ #define TEGRA210_CLK_PLL_M_UD 363 #define TEGRA210_CLK_PLL_C_UD 364 #define TEGRA210_CLK_SCLK_MUX 365 +#define TEGRA210_CLK_PLL_MB_UD 366 +#define TEGRA210_CLK_PLL_P_UD 367 #define TEGRA210_CLK_ACLK 370