[v10,4/5] clk: imx: add imx composite clock

Commit Message

Abel Vesa Oct. 9, 2018, 8:37 a.m. UTC

Since a lot of clocks on imx8m are formed by a mux, gate, predivider and
divider, the idea here is to combine all of those into one composite clock,
but we need to deal with both predivider and divider at the same time and
therefore we add the imx_clk_composite_8m_divider_ops and register
the composite clock with those.

Signed-off-by: Abel Vesa <[e-mail]>
Suggested-by: Sascha Hauer <[e-mail]>
Reviewed-by: Sascha Hauer <[e-mail]>
---
 drivers/clk/imx/Makefile           |   1 +
 drivers/clk/imx/clk-composite-8m.c | 181 +++++++++++++++++++++++++++++++++++++
 drivers/clk/imx/clk.h              |  16 ++++
 3 files changed, 198 insertions(+)
 create mode 100644 drivers/clk/imx/clk-composite-8m.c

Comments

Leonard Crestez Oct. 9, 2018, 10:56 p.m. UTC | #1

On Tue, 2018-10-09 at 08:37 +0000, Abel Vesa wrote:
> +struct clk *imx_clk_composite_8m_flags(const char *name,
> +					const char **parent_names,
> +					int num_parents, void __iomem *reg,
> +					unsigned long flags);
> +
> +#define __imx_clk_composite_8m(name, parent_names, reg, flags) \
> +	imx_clk_composite_8m_flags(name, parent_names, \
> +		ARRAY_SIZE(parent_names), reg, \
> +		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
> +
> +#define imx_clk_composite_8m(name, parent_names, reg) \
> +	__imx_clk_composite_8m(name, parent_names, reg, 0)
> +
> +#define imx_clk_composite_8m_critical(name, parent_names, reg) \
> +	__imx_clk_composite_8m(name, parent_names, reg, CLK_IS_CRITICAL)

Does anyone else think that the "8m" would be prettier next to imx
rather than as a suffix? Using imx8m_clk_composite* and
imx7ulp_clk_composite* makes more sense to me.

--
Regards,
Leonard

Sascha Hauer Oct. 10, 2018, 5:37 a.m. UTC | #2

On Tue, Oct 09, 2018 at 10:56:14PM +0000, Leonard Crestez wrote:
> On Tue, 2018-10-09 at 08:37 +0000, Abel Vesa wrote:
> > +struct clk *imx_clk_composite_8m_flags(const char *name,
> > +					const char **parent_names,
> > +					int num_parents, void __iomem *reg,
> > +					unsigned long flags);
> > +
> > +#define __imx_clk_composite_8m(name, parent_names, reg, flags) \
> > +	imx_clk_composite_8m_flags(name, parent_names, \
> > +		ARRAY_SIZE(parent_names), reg, \
> > +		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
> > +
> > +#define imx_clk_composite_8m(name, parent_names, reg) \
> > +	__imx_clk_composite_8m(name, parent_names, reg, 0)
> > +
> > +#define imx_clk_composite_8m_critical(name, parent_names, reg) \
> > +	__imx_clk_composite_8m(name, parent_names, reg, CLK_IS_CRITICAL)
> 
> Does anyone else think that the "8m" would be prettier next to imx
> rather than as a suffix? Using imx8m_clk_composite* and
> imx7ulp_clk_composite* makes more sense to me.

+1

Sascha

Abel Vesa Oct. 10, 2018, 7:50 a.m. UTC | #3

On Wed, Oct 10, 2018 at 07:37:44AM +0200, Sascha Hauer wrote:
> On Tue, Oct 09, 2018 at 10:56:14PM +0000, Leonard Crestez wrote:
> > On Tue, 2018-10-09 at 08:37 +0000, Abel Vesa wrote:
> > > +struct clk *imx_clk_composite_8m_flags(const char *name,
> > > +					const char **parent_names,
> > > +					int num_parents, void __iomem *reg,
> > > +					unsigned long flags);
> > > +
> > > +#define __imx_clk_composite_8m(name, parent_names, reg, flags) \
> > > +	imx_clk_composite_8m_flags(name, parent_names, \
> > > +		ARRAY_SIZE(parent_names), reg, \
> > > +		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
> > > +
> > > +#define imx_clk_composite_8m(name, parent_names, reg) \
> > > +	__imx_clk_composite_8m(name, parent_names, reg, 0)
> > > +
> > > +#define imx_clk_composite_8m_critical(name, parent_names, reg) \
> > > +	__imx_clk_composite_8m(name, parent_names, reg, CLK_IS_CRITICAL)
> > 
> > Does anyone else think that the "8m" would be prettier next to imx
> > rather than as a suffix? Using imx8m_clk_composite* and
> > imx7ulp_clk_composite* makes more sense to me.
> 
> +1
> 
> Sascha

Just sent another version.

Abel

> 
> -- 
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--

Patch

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index b87513c..237444b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -3,6 +3,7 @@ 
 obj-y += \
 	clk.o \
 	clk-busy.o \
+	clk-composite-8m.o \
 	clk-cpu.o \
 	clk-fixup-div.o \
 	clk-fixup-mux.o \
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
new file mode 100644
index 0000000..a28f6ac
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -0,0 +1,181 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+
+#include "clk.h"
+
+#define PCG_PREDIV_SHIFT	16
+#define PCG_PREDIV_WIDTH	3
+#define PCG_PREDIV_MAX		8
+
+#define PCG_DIV_SHIFT		0
+#define PCG_DIV_WIDTH		6
+#define PCG_DIV_MAX		64
+
+#define PCG_PCS_SHIFT		24
+#define PCG_PCS_MASK		0x7
+
+#define PCG_CGC_SHIFT		28
+
+static unsigned long imx_clk_composite_8m_divider_recalc_rate(struct clk_hw *hw,
+						unsigned long parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned long prediv_rate;
+	unsigned int prediv_value;
+	unsigned int div_value;
+
+	prediv_value = clk_readl(divider->reg) >> divider->shift;
+	prediv_value &= clk_div_mask(divider->width);
+
+	prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
+						NULL, divider->flags,
+						divider->width);
+
+	div_value = clk_readl(divider->reg) >> PCG_DIV_SHIFT;
+	div_value &= clk_div_mask(PCG_DIV_WIDTH);
+
+	return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
+				   divider->flags, PCG_DIV_WIDTH);
+}
+
+static int imx_clk_composite_8m_compute_dividers(unsigned long rate,
+						unsigned long parent_rate,
+						int *prediv, int *postdiv)
+{
+	int div1, div2;
+	int error = INT_MAX;
+	int ret = -EINVAL;
+
+	/* default values */
+	*prediv = 1;
+	*postdiv = 1;
+
+	for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
+		for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
+			int new_error = ((parent_rate / div1) / div2) - rate;
+
+			if (abs(new_error) < abs(error)) {
+				*prediv = div1;
+				*postdiv = div2;
+				error = new_error;
+				ret = 0;
+			}
+		}
+	}
+	return ret;
+}
+
+static long imx_clk_composite_8m_divider_round_rate(struct clk_hw *hw,
+						unsigned long rate,
+						unsigned long *prate)
+{
+	int prediv_value;
+	int div_value;
+
+	imx_clk_composite_8m_compute_dividers(rate, *prate,
+						&prediv_value, &div_value);
+
+	rate = DIV_ROUND_UP(*prate, prediv_value);
+	rate = DIV_ROUND_UP(rate, div_value);
+
+	return rate;
+}
+
+static int imx_clk_composite_8m_divider_set_rate(struct clk_hw *hw,
+					unsigned long rate,
+					unsigned long parent_rate)
+{
+	struct clk_divider *divider = to_clk_divider(hw);
+	unsigned long flags = 0;
+	int prediv_value;
+	int div_value;
+	int ret = 0;
+	u32 val;
+
+	ret = imx_clk_composite_8m_compute_dividers(rate, parent_rate,
+						&prediv_value, &div_value);
+	if (ret)
+		return -EINVAL;
+
+	spin_lock_irqsave(divider->lock, flags);
+
+	val = clk_readl(divider->reg);
+	val &= ~((clk_div_mask(divider->width) << divider->shift) |
+			(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+
+	val |= (u32)(prediv_value  - 1) << divider->shift;
+	val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
+	clk_writel(val, divider->reg);
+
+	spin_unlock_irqrestore(divider->lock, flags);
+
+	return ret;
+}
+
+static const struct clk_ops imx_clk_composite_8m_divider_ops = {
+	.recalc_rate = imx_clk_composite_8m_divider_recalc_rate,
+	.round_rate = imx_clk_composite_8m_divider_round_rate,
+	.set_rate = imx_clk_composite_8m_divider_set_rate,
+};
+
+struct clk *imx_clk_composite_8m_flags(const char *name,
+					const char **parent_names,
+					int num_parents, void __iomem *reg,
+					unsigned long flags)
+{
+	struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
+	struct clk_divider *div = NULL;
+	struct clk_gate *gate = NULL;
+	struct clk_mux *mux = NULL;
+	struct clk *clk = ERR_PTR(-ENOMEM);
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		goto fail;
+
+	mux_hw = &mux->hw;
+	mux->reg = reg;
+	mux->shift = PCG_PCS_SHIFT;
+	mux->mask = PCG_PCS_MASK;
+
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div)
+		goto fail;
+
+	div_hw = &div->hw;
+	div->reg = reg;
+	div->shift = PCG_PREDIV_SHIFT;
+	div->width = PCG_PREDIV_WIDTH;
+	div->lock = &imx_ccm_lock;
+	div->flags = CLK_DIVIDER_ROUND_CLOSEST;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		goto fail;
+
+	gate_hw = &gate->hw;
+	gate->reg = reg;
+	gate->bit_idx = PCG_CGC_SHIFT;
+
+	clk = clk_register_composite(NULL, name, parent_names, num_parents,
+					mux_hw, &clk_mux_ops, div_hw,
+					&imx_clk_composite_8m_divider_ops,
+					gate_hw, &clk_gate_ops, flags);
+	if (IS_ERR(clk))
+		goto fail;
+
+	return clk;
+
+fail:
+	kfree(gate);
+	kfree(div);
+	kfree(mux);
+	return clk;
+}
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 12b3fd6..37c8c4a 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -232,4 +232,20 @@  struct clk *imx_clk_cpu(const char *name, const char *parent_name,
 		struct clk *div, struct clk *mux, struct clk *pll,
 		struct clk *step);
 
+struct clk *imx_clk_composite_8m_flags(const char *name,
+					const char **parent_names,
+					int num_parents, void __iomem *reg,
+					unsigned long flags);
+
+#define __imx_clk_composite_8m(name, parent_names, reg, flags) \
+	imx_clk_composite_8m_flags(name, parent_names, \
+		ARRAY_SIZE(parent_names), reg, \
+		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
+#define imx_clk_composite_8m(name, parent_names, reg) \
+	__imx_clk_composite_8m(name, parent_names, reg, 0)
+
+#define imx_clk_composite_8m_critical(name, parent_names, reg) \
+	__imx_clk_composite_8m(name, parent_names, reg, CLK_IS_CRITICAL)
+
 #endif