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[81.47.145.58]) by smtp.gmail.com with ESMTPSA id h12sm28878113wma.48.2018.12.17.01.46.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Dec 2018 01:46:36 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, sboyd@kernel.org, will.deacon@arm.com, mturquette@baylibre.com, jassisinghbrar@gmail.com Cc: bjorn.andersson@linaro.org, vkoul@kernel.org, niklas.cassel@linaro.org, sibis@codeaurora.org, georgi.djakov@linaro.org, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 01/13] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency Date: Mon, 17 Dec 2018 10:46:18 +0100 Message-Id: <1545039990-19984-2-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1545039990-19984-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- drivers/clk/qcom/gcc-qcs404.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 64da032..833436a 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -304,10 +304,16 @@ static struct clk_alpha_pll gpll0_out_main = { }, }; +static const struct pll_vco gpll0_ao_out_vco[] = { + { 800000000, 800000000, 0 }, +}; + static struct clk_alpha_pll gpll0_ao_out_main = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .flags = SUPPORTS_FSM_MODE, + .vco_table = gpll0_ao_out_vco, + .num_vco = ARRAY_SIZE(gpll0_ao_out_vco), .clkr = { .enable_reg = 0x45000, .enable_mask = BIT(0),