Message ID | 1556169264-31683-1-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | [1/2] clk: imx7ulp: update nic1_bus_clk parent info | expand |
Quoting Anson Huang (2019-04-24 22:19:07) > Since i.MX7ULP B0 chip, nic1_bus_clk's parent is changed to > from nic0_clk directly, update it accordingly. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Looks ok. Shawn, will you pick it up?
On Thu, Apr 25, 2019 at 05:03:31PM -0700, Stephen Boyd wrote: > Quoting Anson Huang (2019-04-24 22:19:07) > > Since i.MX7ULP B0 chip, nic1_bus_clk's parent is changed to > > from nic0_clk directly, update it accordingly. > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > Looks ok. Shawn, will you pick it up? Stephen, I prefer you directly pick up any i.MX clock patches that look good, after I already send you PR. I will start again for next cycle around -rc1. Shawn
Quoting Shawn Guo (2019-04-25 20:20:04) > On Thu, Apr 25, 2019 at 05:03:31PM -0700, Stephen Boyd wrote: > > Quoting Anson Huang (2019-04-24 22:19:07) > > > Since i.MX7ULP B0 chip, nic1_bus_clk's parent is changed to > > > from nic0_clk directly, update it accordingly. > > > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > > > Looks ok. Shawn, will you pick it up? > > Stephen, > > I prefer you directly pick up any i.MX clock patches that look good, > after I already send you PR. I will start again for next cycle > around -rc1. > Ok. Thanks for letting me know.
diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 6668210..42e4667 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -115,7 +115,7 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) clks[IMX7ULP_CLK_NIC0_DIV] = imx_clk_hw_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); clks[IMX7ULP_CLK_NIC1_DIV] = imx_clk_hw_divider_flags("nic1_clk", "nic0_clk", base + 0x40, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); - clks[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_hw_divider_flags("nic1_bus_clk", "nic1_clk", base + 0x40, 4, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); + clks[IMX7ULP_CLK_NIC1_BUS_DIV] = imx_clk_hw_divider_flags("nic1_bus_clk", "nic0_clk", base + 0x40, 4, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4);
Since i.MX7ULP B0 chip, nic1_bus_clk's parent is changed to from nic0_clk directly, update it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx7ulp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)