| Message ID | 1556645270-20648-3-git-send-email-aisheng.dong@nxp.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | clk: imx: scu: add parsing clocks from device tree support | expand |
On 30.04.2019 20:35, Aisheng Dong wrote: > MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside > in different subsystems across CPUs and also vary a bit on the availability. > > Same as SCU clock, we want to move the clock definition into device tree > which can fully decouple the dependency of Clock ID definition from device > tree and make us be able to write a fully generic lpcg clock driver. > > And we can also use the existence of clock nodes in device tree to address > the device and clock availability differences across different SoCs. > > diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > Required properties: > +- compatible: Should be one of: > + "fsl,imx8qxp-lpcg" > + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". > +- reg: Address and length of the register set. > +- #clock-cells: Should be 1. One LPCG supports multiple clocks. > +- clocks: Input parent clocks phandle array for each clock. > +- bit-offset: An integer array indicating the bit offset for each clock. > +- hw-autogate: Boolean array indicating whether supports HW autogate for > + each clock. > +- clock-output-names: Shall be the corresponding names of the outputs. > + NOTE this property must be specified in the same order > + as the clock bit-offset and hw-autogate property. Splitting the LPCG areas is good but describing "bit-offset" and similar inside devicetree seems excessively generic. Perhaps we could have many smaller imx8qxp-lpcg-sdhc, imx8qxp-lpcg-enet etc where the actual clks inside each node are still defined in driver code. > usdhc1: mmc@5b010000 { > @@ -44,8 +66,8 @@ usdhc1: mmc@5b010000 { > interrupt-parent = <&gic>; > interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; > reg = <0x5b010000 0x10000>; > - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, > - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, > - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; > + clocks = <&sdhc0_lpcg 1>, > + <&sdhc0_lpcg 0>, > + <&sdhc0_lpcg 2>; This is less readable, can't we keep symbolic constants?
> From: Leonard Crestez > Sent: Monday, May 20, 2019 7:45 PM > > On 30.04.2019 20:35, Aisheng Dong wrote: > > MX8QM and MX8QXP LPCG Clocks are mostly the same except they may > > reside in different subsystems across CPUs and also vary a bit on the > availability. > > > > Same as SCU clock, we want to move the clock definition into device > > tree which can fully decouple the dependency of Clock ID definition > > from device tree and make us be able to write a fully generic lpcg clock > driver. > > > > And we can also use the existence of clock nodes in device tree to > > address the device and clock availability differences across different SoCs. > > > > diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt > > > > Required properties: > > +- compatible: Should be one of: > > + "fsl,imx8qxp-lpcg" > > + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". > > +- reg: Address and length of the register set. > > +- #clock-cells: Should be 1. One LPCG supports multiple clocks. > > +- clocks: Input parent clocks phandle array for each clock. > > +- bit-offset: An integer array indicating the bit offset for each clock. > > +- hw-autogate: Boolean array indicating whether supports HW > autogate for > > + each clock. > > +- clock-output-names: Shall be the corresponding names of the outputs. > > + NOTE this property must be specified in the same order > > + as the clock bit-offset and hw-autogate property. > > Splitting the LPCG areas is good but describing "bit-offset" and similar inside > devicetree seems excessively generic. > > Perhaps we could have many smaller imx8qxp-lpcg-sdhc, imx8qxp-lpcg-enet > etc where the actual clks inside each node are still defined in driver code. > If that way, we would have too many more compatible strings per clocks and we have to add more for new SoCs which I'd like to avoid. > > usdhc1: mmc@5b010000 { > > @@ -44,8 +66,8 @@ usdhc1: mmc@5b010000 { > > interrupt-parent = <&gic>; > > interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; > > reg = <0x5b010000 0x10000>; > > - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, > > - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, > > - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; > > + clocks = <&sdhc0_lpcg 1>, > > + <&sdhc0_lpcg 0>, > > + <&sdhc0_lpcg 2>; > > This is less readable, can't we keep symbolic constants? I'm scared to define more macros for device clocks. It's usually a one time job and could be referenced easily by looking into the definition of sdhc0_lpcg in DT. So less readable may not be a real problem. Regards Dong Aisheng
diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt index 965cfa4..6fc2fd8 100644 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt @@ -11,6 +11,21 @@ enabled by these control bits, it might still not be running based on the base resource. Required properties: +- compatible: Should be one of: + "fsl,imx8qxp-lpcg" + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". +- reg: Address and length of the register set. +- #clock-cells: Should be 1. One LPCG supports multiple clocks. +- clocks: Input parent clocks phandle array for each clock. +- bit-offset: An integer array indicating the bit offset for each clock. +- hw-autogate: Boolean array indicating whether supports HW autogate for + each clock. +- clock-output-names: Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock bit-offset and hw-autogate property. +- power-domains: Should contain the power domain used by this clock. + +Legacy binding (DEPRECATED): - compatible: Should be one of: "fsl,imx8qxp-lpcg-adma", "fsl,imx8qxp-lpcg-conn", @@ -33,10 +48,17 @@ Examples: #include <dt-bindings/clock/imx8qxp-clock.h> -conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; +sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; #clock-cells = <1>; + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; }; usdhc1: mmc@5b010000 { @@ -44,8 +66,8 @@ usdhc1: mmc@5b010000 { interrupt-parent = <&gic>; interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; };
MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside in different subsystems across CPUs and also vary a bit on the availability. Same as SCU clock, we want to move the clock definition into device tree which can fully decouple the dependency of Clock ID definition from device tree and make us be able to write a fully generic lpcg clock driver. And we can also use the existence of clock nodes in device tree to address the device and clock availability differences across different SoCs. Cc: Rob Herring <robh+dt@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- ChangeLog: v1->v2: * Update example * Add power domain property --- .../devicetree/bindings/clock/imx8qxp-lpcg.txt | 34 ++++++++++++++++++---- 1 file changed, 28 insertions(+), 6 deletions(-)