| Message ID | 1557339895-21952-4-git-send-email-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | clk: qcom: Misc updates for Root Clock Generators | expand |
Quoting Taniya Das (2019-05-08 11:24:55) > Update the init data name for each of the dynamic frequency switch > controlled clock associated with the RCG clock name, so that it can be > generated as per the hardware plan. Thus update the macro accordingly. > > Signed-off-by: Taniya Das <tdas@codeaurora.org> This patch doesn't make any sense to me. > --- > drivers/clk/qcom/clk-rcg.h | 2 +- > drivers/clk/qcom/gcc-sdm845.c | 96 +++++++++++++++++++++---------------------- > 2 files changed, 49 insertions(+), 49 deletions(-) > > diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h > index 5562f38..e40e8f8 100644 > --- a/drivers/clk/qcom/clk-rcg.h > +++ b/drivers/clk/qcom/clk-rcg.h > @@ -171,7 +171,7 @@ struct clk_rcg_dfs_data { > }; > > #define DEFINE_RCG_DFS(r) \ > - { .rcg = &r##_src, .init = &r##_init } > + { .rcg = &r, .init = &r##_init } Why do we need to rename the init data? > > extern int qcom_cc_register_rcg_dfs(struct regmap *regmap, > const struct clk_rcg_dfs_data *rcgs, > diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c > index 7131dcf..a76178b 100644 > --- a/drivers/clk/qcom/gcc-sdm845.c > +++ b/drivers/clk/qcom/gcc-sdm845.c > @@ -408,7 +408,7 @@ enum { > { } > }; > > -static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = { > +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { > .name = "gcc_qupv3_wrap0_s0_clk_src", > .parent_names = gcc_parent_names_0, > .num_parents = 4, > @@ -3577,22 +3577,22 @@ enum { > MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); > > static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { > - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk), > + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), I've trimmed the above to try and see what's changed but it doesn't make sense still.
Hello Stephen, Thanks for the review. On 5/9/2019 10:57 PM, Stephen Boyd wrote: > Quoting Taniya Das (2019-05-08 11:24:55) >> Update the init data name for each of the dynamic frequency switch >> controlled clock associated with the RCG clock name, so that it can be >> generated as per the hardware plan. Thus update the macro accordingly. >> >> Signed-off-by: Taniya Das <tdas@codeaurora.org> > > This patch doesn't make any sense to me. > >> --- >> drivers/clk/qcom/clk-rcg.h | 2 +- >> drivers/clk/qcom/gcc-sdm845.c | 96 +++++++++++++++++++++---------------------- >> 2 files changed, 49 insertions(+), 49 deletions(-) >> >> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h >> index 5562f38..e40e8f8 100644 >> --- a/drivers/clk/qcom/clk-rcg.h >> +++ b/drivers/clk/qcom/clk-rcg.h >> @@ -171,7 +171,7 @@ struct clk_rcg_dfs_data { >> }; >> >> #define DEFINE_RCG_DFS(r) \ >> - { .rcg = &r##_src, .init = &r##_init } >> + { .rcg = &r, .init = &r##_init } > > Why do we need to rename the init data? > We want to manage the init data as the clock source name, so that we could manage to auto generate our code. So that we do not have to re-name the clock init data manually if the DFS source names gets updated at any point of time. >> >> extern int qcom_cc_register_rcg_dfs(struct regmap *regmap, >> const struct clk_rcg_dfs_data *rcgs, >> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c >> index 7131dcf..a76178b 100644 >> --- a/drivers/clk/qcom/gcc-sdm845.c >> +++ b/drivers/clk/qcom/gcc-sdm845.c >> @@ -408,7 +408,7 @@ enum { >> { } >> }; >> >> -static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = { >> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { >> .name = "gcc_qupv3_wrap0_s0_clk_src", >> .parent_names = gcc_parent_names_0, >> .num_parents = 4, >> @@ -3577,22 +3577,22 @@ enum { >> MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); >> >> static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { >> - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk), >> + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), > > I've trimmed the above to try and see what's changed but it doesn't make > sense still. >
Quoting Taniya Das (2019-05-09 19:58:39) > Hello Stephen, > > Thanks for the review. > > On 5/9/2019 10:57 PM, Stephen Boyd wrote: > > Quoting Taniya Das (2019-05-08 11:24:55) > >> Update the init data name for each of the dynamic frequency switch > >> controlled clock associated with the RCG clock name, so that it can be > >> generated as per the hardware plan. Thus update the macro accordingly. > >> > >> Signed-off-by: Taniya Das <tdas@codeaurora.org> > > > > This patch doesn't make any sense to me. > > > >> --- > >> drivers/clk/qcom/clk-rcg.h | 2 +- > >> drivers/clk/qcom/gcc-sdm845.c | 96 +++++++++++++++++++++---------------------- > >> 2 files changed, 49 insertions(+), 49 deletions(-) > >> > >> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h > >> index 5562f38..e40e8f8 100644 > >> --- a/drivers/clk/qcom/clk-rcg.h > >> +++ b/drivers/clk/qcom/clk-rcg.h > >> @@ -171,7 +171,7 @@ struct clk_rcg_dfs_data { > >> }; > >> > >> #define DEFINE_RCG_DFS(r) \ > >> - { .rcg = &r##_src, .init = &r##_init } > >> + { .rcg = &r, .init = &r##_init } > > > > Why do we need to rename the init data? > > > > We want to manage the init data as the clock source name, so that we > could manage to auto generate our code. So that we do not have to > re-name the clock init data manually if the DFS source names gets > updated at any point of time. > Why is the clk name changing to not have a _src after the "root" of the clk name? As long as I can remember, RCGs have a "_src" postfix.
Hello Stephen, On 5/10/2019 11:24 PM, Stephen Boyd wrote: > Quoting Taniya Das (2019-05-09 19:58:39) >> Hello Stephen, >> >> Thanks for the review. >> >> On 5/9/2019 10:57 PM, Stephen Boyd wrote: >>> Quoting Taniya Das (2019-05-08 11:24:55) >>>> Update the init data name for each of the dynamic frequency switch >>>> controlled clock associated with the RCG clock name, so that it can be >>>> generated as per the hardware plan. Thus update the macro accordingly. >>>> >>>> Signed-off-by: Taniya Das <tdas@codeaurora.org> >>> >>> This patch doesn't make any sense to me. >>> >>>> --- >>>> drivers/clk/qcom/clk-rcg.h | 2 +- >>>> drivers/clk/qcom/gcc-sdm845.c | 96 +++++++++++++++++++++---------------------- >>>> 2 files changed, 49 insertions(+), 49 deletions(-) >>>> >>>> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h >>>> index 5562f38..e40e8f8 100644 >>>> --- a/drivers/clk/qcom/clk-rcg.h >>>> +++ b/drivers/clk/qcom/clk-rcg.h >>>> @@ -171,7 +171,7 @@ struct clk_rcg_dfs_data { >>>> }; >>>> >>>> #define DEFINE_RCG_DFS(r) \ >>>> - { .rcg = &r##_src, .init = &r##_init } >>>> + { .rcg = &r, .init = &r##_init } >>> >>> Why do we need to rename the init data? >>> >> >> We want to manage the init data as the clock source name, so that we >> could manage to auto generate our code. So that we do not have to >> re-name the clock init data manually if the DFS source names gets >> updated at any point of time. >> > > Why is the clk name changing to not have a _src after the "root" of the > clk name? As long as I can remember, RCGs have a "_src" postfix. > Yes, the RCGs would have _src, so we do want the init data also to be generated with _src postfix. So that we do not have to manually clean up the generated code.
Quoting Taniya Das (2019-05-12 20:44:46) > On 5/10/2019 11:24 PM, Stephen Boyd wrote: > >>>> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h > >>>> index 5562f38..e40e8f8 100644 > >>>> --- a/drivers/clk/qcom/clk-rcg.h > >>>> +++ b/drivers/clk/qcom/clk-rcg.h > >>>> @@ -171,7 +171,7 @@ struct clk_rcg_dfs_data { > >>>> }; > >>>> > >>>> #define DEFINE_RCG_DFS(r) \ > >>>> - { .rcg = &r##_src, .init = &r##_init } > >>>> + { .rcg = &r, .init = &r##_init } > >>> > >>> Why do we need to rename the init data? > >>> > >> > >> We want to manage the init data as the clock source name, so that we > >> could manage to auto generate our code. So that we do not have to > >> re-name the clock init data manually if the DFS source names gets > >> updated at any point of time. > >> > > > > Why is the clk name changing to not have a _src after the "root" of the > > clk name? As long as I can remember, RCGs have a "_src" postfix. > > > > Yes, the RCGs would have _src, so we do want the init data also to be > generated with _src postfix. So that we do not have to manually clean up > the generated code. > Please manually cleanup the generated code, or fix the code generator to do what you want.
Hello Stephen, Thanks for the review. On 7/16/2019 4:14 AM, Stephen Boyd wrote: > Quoting Taniya Das (2019-05-12 20:44:46) >> On 5/10/2019 11:24 PM, Stephen Boyd wrote: >>>>>> diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h >>>>>> index 5562f38..e40e8f8 100644 >>>>>> --- a/drivers/clk/qcom/clk-rcg.h >>>>>> +++ b/drivers/clk/qcom/clk-rcg.h >>>>>> @@ -171,7 +171,7 @@ struct clk_rcg_dfs_data { >>>>>> }; >>>>>> >>>>>> #define DEFINE_RCG_DFS(r) \ >>>>>> - { .rcg = &r##_src, .init = &r##_init } >>>>>> + { .rcg = &r, .init = &r##_init } >>>>> >>>>> Why do we need to rename the init data? >>>>> >>>> >>>> We want to manage the init data as the clock source name, so that we >>>> could manage to auto generate our code. So that we do not have to >>>> re-name the clock init data manually if the DFS source names gets >>>> updated at any point of time. >>>> >>> >>> Why is the clk name changing to not have a _src after the "root" of the >>> clk name? As long as I can remember, RCGs have a "_src" postfix. >>> >> >> Yes, the RCGs would have _src, so we do want the init data also to be >> generated with _src postfix. So that we do not have to manually clean up >> the generated code. >> > > Please manually cleanup the generated code, or fix the code > generator to do what you want. > Fixing the code manually is not what we intend to do and it is time consuming with too many DFS controlled clocks. This really helps us align to internal code.
Quoting Taniya Das (2019-07-15 21:22:02) > Hello Stephen, > > Thanks for the review. > > On 7/16/2019 4:14 AM, Stephen Boyd wrote: > > Quoting Taniya Das (2019-05-12 20:44:46) > >> On 5/10/2019 11:24 PM, Stephen Boyd wrote: > >>> Why is the clk name changing to not have a _src after the "root" of the > >>> clk name? As long as I can remember, RCGs have a "_src" postfix. > >>> > >> > >> Yes, the RCGs would have _src, so we do want the init data also to be > >> generated with _src postfix. So that we do not have to manually clean up > >> the generated code. > >> > > > > Please manually cleanup the generated code, or fix the code > > generator to do what you want. > > > > Fixing the code manually is not what we intend to do and it is time > consuming with too many DFS controlled clocks. This really helps us > align to internal code. > And you can't fix the code generator to drop the _src part of whatever is spit out for the DFS lines?
On 7/17/2019 4:52 AM, Stephen Boyd wrote: > Quoting Taniya Das (2019-07-15 21:22:02) >> Hello Stephen, >> >> Thanks for the review. >> >> On 7/16/2019 4:14 AM, Stephen Boyd wrote: >>> Quoting Taniya Das (2019-05-12 20:44:46) >>>> On 5/10/2019 11:24 PM, Stephen Boyd wrote: >>>>> Why is the clk name changing to not have a _src after the "root" of the >>>>> clk name? As long as I can remember, RCGs have a "_src" postfix. >>>>> >>>> >>>> Yes, the RCGs would have _src, so we do want the init data also to be >>>> generated with _src postfix. So that we do not have to manually clean up >>>> the generated code. >>>> >>> >>> Please manually cleanup the generated code, or fix the code >>> generator to do what you want. >>> >> >> Fixing the code manually is not what we intend to do and it is time >> consuming with too many DFS controlled clocks. This really helps us >> align to internal code. >> > > And you can't fix the code generator to drop the _src part of whatever > is spit out for the DFS lines? > Sure, will drop this.
Quoting Taniya Das (2019-07-30 03:51:07) > > > On 7/17/2019 4:52 AM, Stephen Boyd wrote: > > Quoting Taniya Das (2019-07-15 21:22:02) > >> Hello Stephen, > >> > >> Thanks for the review. > >> > >> On 7/16/2019 4:14 AM, Stephen Boyd wrote: > >>> Quoting Taniya Das (2019-05-12 20:44:46) > >>>> On 5/10/2019 11:24 PM, Stephen Boyd wrote: > >>>>> Why is the clk name changing to not have a _src after the "root" of the > >>>>> clk name? As long as I can remember, RCGs have a "_src" postfix. > >>>>> > >>>> > >>>> Yes, the RCGs would have _src, so we do want the init data also to be > >>>> generated with _src postfix. So that we do not have to manually clean up > >>>> the generated code. > >>>> > >>> > >>> Please manually cleanup the generated code, or fix the code > >>> generator to do what you want. > >>> > >> > >> Fixing the code manually is not what we intend to do and it is time > >> consuming with too many DFS controlled clocks. This really helps us > >> align to internal code. > >> > > > > And you can't fix the code generator to drop the _src part of whatever > > is spit out for the DFS lines? > > > > Sure, will drop this. > Actually, I'm OK with this patch, but I'd like to see it in a larger series that introduces another clk driver using this macro. The reason I like it is that I can search for the same string name and find the clk that has DFS enabled on it, instead of finding the branch which doesn't have DFS. Sorry for the back and forth, I got confused about what was going on.
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 5562f38..e40e8f8 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -171,7 +171,7 @@ struct clk_rcg_dfs_data { }; #define DEFINE_RCG_DFS(r) \ - { .rcg = &r##_src, .init = &r##_init } + { .rcg = &r, .init = &r##_init } extern int qcom_cc_register_rcg_dfs(struct regmap *regmap, const struct clk_rcg_dfs_data *rcgs, diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c index 7131dcf..a76178b 100644 --- a/drivers/clk/qcom/gcc-sdm845.c +++ b/drivers/clk/qcom/gcc-sdm845.c @@ -408,7 +408,7 @@ enum { { } }; -static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = { +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -421,10 +421,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = { +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -437,10 +437,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = { +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -453,10 +453,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = { +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -469,10 +469,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = { +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -485,10 +485,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = { +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -501,10 +501,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = { +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { .name = "gcc_qupv3_wrap0_s6_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -517,10 +517,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = { +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { .name = "gcc_qupv3_wrap0_s7_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -533,10 +533,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = { +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { .name = "gcc_qupv3_wrap1_s0_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -549,10 +549,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = { +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { .name = "gcc_qupv3_wrap1_s1_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -565,10 +565,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = { +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { .name = "gcc_qupv3_wrap1_s2_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -581,10 +581,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = { +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { .name = "gcc_qupv3_wrap1_s3_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -597,10 +597,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = { +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { .name = "gcc_qupv3_wrap1_s4_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -613,10 +613,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = { +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { .name = "gcc_qupv3_wrap1_s5_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -629,10 +629,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = { +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { .name = "gcc_qupv3_wrap1_s6_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -645,10 +645,10 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, }; -static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = { +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { .name = "gcc_qupv3_wrap1_s7_clk_src", .parent_names = gcc_parent_names_0, .num_parents = 4, @@ -661,7 +661,7 @@ enum { .hid_width = 5, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init, + .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, }; static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { @@ -3577,22 +3577,22 @@ enum { MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table); static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk), - DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), }; static int gcc_sdm845_probe(struct platform_device *pdev)
Update the init data name for each of the dynamic frequency switch controlled clock associated with the RCG clock name, so that it can be generated as per the hardware plan. Thus update the macro accordingly. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/clk-rcg.h | 2 +- drivers/clk/qcom/gcc-sdm845.c | 96 +++++++++++++++++++++---------------------- 2 files changed, 49 insertions(+), 49 deletions(-) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.