From patchwork Mon Jun 24 03:02:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11012057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30F1C1580 for ; Mon, 24 Jun 2019 03:04:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 226E928AF8 for ; Mon, 24 Jun 2019 03:04:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 167AD28B08; Mon, 24 Jun 2019 03:04:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A8A7828AF8 for ; Mon, 24 Jun 2019 03:04:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727042AbfFXDDn (ORCPT ); Sun, 23 Jun 2019 23:03:43 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17314 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727545AbfFXDDm (ORCPT ); Sun, 23 Jun 2019 23:03:42 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 23 Jun 2019 20:03:40 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 23 Jun 2019 20:03:41 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 23 Jun 2019 20:03:41 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 24 Jun 2019 03:03:41 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 24 Jun 2019 03:03:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 24 Jun 2019 03:03:40 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.174.126]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 23 Jun 2019 20:03:41 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH V4 13/18] soc/tegra: pmc: allow support for more tegra wake Date: Sun, 23 Jun 2019 20:02:54 -0700 Message-ID: <1561345379-2429-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1561345379-2429-1-git-send-email-skomatineni@nvidia.com> References: <1561345379-2429-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561345420; bh=4EGQI++zj4lUDjQs0M1vegh7zzNvu5bAdmZ5kricB/0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=EYKXHL/fZIwVDvujMVzoUXptHAiacdUIgNtbpK+2/bFznSOyOaqGaz3d0F8Bxdrmz vAviRpxdlaCu1vPYt+Gga3frJFj7gKxPENbM7Uz0IeB0rFsSzonCmDxhnLpTxglbiS 4RT6HYtzAuwL2ScQxMsjYEnOqa81Cb3swEVfABIDtIoG2ZJ87zBz2idEusfqVVMs6J Q/kd5IUiGJ4vIktEszSbbxzWBnLiEQnooE69efAGtScV5dKoOP0fVu5WWBuF4rLbR7 h05C1OI1mZZxBn5K/xGmmKAfmL/1skJNzr72uaHKxGnuq1CLFZEvRYnNqOwjXGeNYT qYOl/p7Iv95Yg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch allows to create separate irq_set_wake and irq_set_type implementations for different tegra designs PMC that has different wake models which require difference wake registers and different programming sequence. AOWAKE model support is available for Tegra186 and Tegra194 only and it resides within PMC and supports tiered wake architecture. Tegra210 and prior tegra designs uses PMC directly to receive wake events and coordinate the wake sequence. Signed-off-by: Sowjanya Komatineni --- drivers/soc/tegra/pmc.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index edd4fe06810f..e87f29a35fcf 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -226,6 +226,8 @@ struct tegra_pmc_soc { void (*setup_irq_polarity)(struct tegra_pmc *pmc, struct device_node *np, bool invert); + int (*irq_set_wake)(struct irq_data *data, unsigned int on); + int (*irq_set_type)(struct irq_data *data, unsigned int type); const char * const *reset_sources; unsigned int num_reset_sources; @@ -1919,7 +1921,7 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { .alloc = tegra_pmc_irq_alloc, }; -static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) +static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); unsigned int offset, bit; @@ -1951,7 +1953,7 @@ static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) return 0; } -static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) +static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); u32 value; @@ -2005,8 +2007,10 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc) pmc->irq.irq_unmask = irq_chip_unmask_parent; pmc->irq.irq_eoi = irq_chip_eoi_parent; pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; - pmc->irq.irq_set_type = tegra_pmc_irq_set_type; - pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; + if (pmc->soc->irq_set_type) + pmc->irq.irq_set_type = pmc->soc->irq_set_type; + if (pmc->soc->irq_set_wake) + pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, &tegra_pmc_irq_domain_ops, pmc); @@ -2679,6 +2683,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .regs = &tegra186_pmc_regs, .init = NULL, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .irq_set_wake = tegra186_pmc_irq_set_wake, + .irq_set_type = tegra186_pmc_irq_set_type, .reset_sources = tegra186_reset_sources, .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), .reset_levels = tegra186_reset_levels,