Message ID | 1572515888-3385-3-git-send-email-peng.fan@nxp.com (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | clk: imx: imx7d: move setting clk parent to dts | expand |
Hi Peng, On Thu, Oct 31, 2019 at 7:02 AM Peng Fan <peng.fan@nxp.com> wrote: > > From: Peng Fan <peng.fan@nxp.com> > > Since the set parent could be done by assigned-clock-parents in > dts, so no need clk_set_parent in driver. It looks like this will cause breakage if someone is using an old dtb, right? We try not to break existing dtbs.
> Subject: Re: [PATCH 2/2] clk: imx: imx7d: remove clk_set_parent > > Hi Peng, > > On Thu, Oct 31, 2019 at 7:02 AM Peng Fan <peng.fan@nxp.com> wrote: > > > > From: Peng Fan <peng.fan@nxp.com> > > > > Since the set parent could be done by assigned-clock-parents in dts, > > so no need clk_set_parent in driver. > > It looks like this will cause breakage if someone is using an old dtb, right? Yes. > > We try not to break existing dtbs. ok. Then there will be lots code in tree for compatibility. Thanks, Peng.
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 0c9f7adb41ae..b73e3e148497 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -878,18 +878,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); - clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk); - clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk); - clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk); - clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk); - clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk); - clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk); - - clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); - - /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ - clk_set_parent(hws[IMX7D_GPT1_ROOT_SRC]->clk, hws[IMX7D_OSC_24M_CLK]->clk); - /* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */ hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1); hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);