| Message ID | 1573117429-9175-1-git-send-email-rajan.vaja@xilinx.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | clk: zynqmp: Extend driver for versal | expand |
Quoting Rajan Vaja (2019-11-07 01:03:49) > Add Versal compatible string to support Versal > binding. > > Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> > Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- Can you send this as a patch series instead of a collection of different patches all sent individually? It's hard to track the topics without proper threading in my MUA. > drivers/clk/zynqmp/clkc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c index a11f93e..10e89f2 100644 --- a/drivers/clk/zynqmp/clkc.c +++ b/drivers/clk/zynqmp/clkc.c @@ -2,7 +2,7 @@ /* * Zynq UltraScale+ MPSoC clock controller * - * Copyright (C) 2016-2018 Xilinx + * Copyright (C) 2016-2019 Xilinx * * Based on drivers/clk/zynq/clkc.c */ @@ -749,6 +749,7 @@ static int zynqmp_clock_probe(struct platform_device *pdev) static const struct of_device_id zynqmp_clock_of_match[] = { {.compatible = "xlnx,zynqmp-clk"}, + {.compatible = "xlnx,versal-clk"}, {}, }; MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);