From patchwork Tue Nov 19 06:50:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11250943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DEC97930 for ; Tue, 19 Nov 2019 06:52:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BE0E0222ED for ; Tue, 19 Nov 2019 06:52:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Cu/4rNAG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727741AbfKSGvF (ORCPT ); Tue, 19 Nov 2019 01:51:05 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:10804 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727575AbfKSGvE (ORCPT ); Tue, 19 Nov 2019 01:51:04 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 18 Nov 2019 22:51:06 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 18 Nov 2019 22:51:03 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 18 Nov 2019 22:51:03 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:51:03 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 19 Nov 2019 06:51:03 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.254]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 18 Nov 2019 22:51:03 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v1 08/17] clk: tegra: Use Tegra PMC helper function for PLLE IDDQ Date: Mon, 18 Nov 2019 22:50:25 -0800 Message-ID: <1574146234-3871-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574146266; bh=2gZW9nYdzkXkyTc5bBk/WveG4zN9ZQjJdfxaExNTDSc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Cu/4rNAGo+PfmjejTL4sGQT42og6qZzdi+71bYE393qKBBvw5BM1AgpZebJgQ7V8E 4kLCONQPkjhFLglkh0vaTwH3QJHpRnsYhajwuaf6/tgdGrw8aBZcA+gUoYCHTlU2Sj 1ta5ylz4etZ5vy99B7h8JXxurplN3Ogp980hcZZrWx2OBkZfUVUSRhDYG0Oma+HHTf OItDek0dyABqpJgfeeTNhogM8oG+YzORXKCnOyvX+t4KtNI1d7ZhElI/Tw7fMApStu UjEakwhPrawPH5Ikli8RJhWcMlh1RkMOhSoKDoMNhv9pH6rSKi+W5vHPPXRD3YVwTJ QN7SbbzsGBemA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra PMC has PLLE IDDQ programming to bring the PLLE pads out of DPD idle state through software by overriding the hardware control. Currently Tegra clock driver programs Tegra PMC registers directly for enabling software override and to bring PLLE pads out of DPD idle state. With this, when Tegra PMC is in secure mode, any direct PMC register access from non-secure world will not go through. This patch updates Tegra clock driver to use Tegra PMC helper function to clear PLLE IDDQ through software control that does PMC programming using tegra_pmc_writel and tegra_pmc_readl which supports both secure mode and non-secure mode PMC access. Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-pll.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index f3c0a637174f..4ae9e282e7be 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -143,10 +143,6 @@ #define PLLCX_MISC2_DEFAULT 0x30211200 #define PLLCX_MISC3_DEFAULT 0x200 -#define PMC_SATA_PWRGT 0x1ac -#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) -#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) - #define PLLSS_MISC_KCP 0 #define PLLSS_MISC_KVCO 0 #define PLLSS_MISC_SETUP 0 @@ -863,24 +859,11 @@ static int clk_plle_training(struct tegra_clk_pll *pll) u32 val; unsigned long timeout; - if (!pll->pmc) - return -ENOSYS; - /* * PLLE is already disabled, and setup cleared; * create falling edge on PLLE IDDQ input. */ - val = readl(pll->pmc + PMC_SATA_PWRGT); - val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; - writel(val, pll->pmc + PMC_SATA_PWRGT); - - val = readl(pll->pmc + PMC_SATA_PWRGT); - val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; - writel(val, pll->pmc + PMC_SATA_PWRGT); - - val = readl(pll->pmc + PMC_SATA_PWRGT); - val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; - writel(val, pll->pmc + PMC_SATA_PWRGT); + tegra_pmc_clear_plle_iddq(); val = pll_readl_misc(pll);