From patchwork Tue Jan 14 07:24:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11331403 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8044D13A0 for ; Tue, 14 Jan 2020 07:24:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5DCF4222C4 for ; Tue, 14 Jan 2020 07:24:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="rykc2x8E" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729149AbgANHYo (ORCPT ); Tue, 14 Jan 2020 02:24:44 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:13262 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729129AbgANHYo (ORCPT ); Tue, 14 Jan 2020 02:24:44 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 Jan 2020 23:23:49 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 13 Jan 2020 23:24:43 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 13 Jan 2020 23:24:43 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 14 Jan 2020 07:24:42 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 14 Jan 2020 07:24:42 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.169.242]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 13 Jan 2020 23:24:42 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v8 17/22] ASoC: nau8825: change Tegra clk_out_2 provider to tegra_pmc Date: Mon, 13 Jan 2020 23:24:22 -0800 Message-ID: <1578986667-16041-18-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578986667-16041-1-git-send-email-skomatineni@nvidia.com> References: <1578986667-16041-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578986629; bh=pWNZAo13Br7GvFxHxRFIS/1sozX6HF632kX/lxY43iQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=rykc2x8E9KoeCszN8vs2smSy3V/kR1R6KO2wQH7JzY8CHfR+fOB22rgxYlOuVPZwX nxa0iS4xlhZEPcTeEtdlslY8+/ZXH1SzyTgSuu77UuHgZnBKFhLuvb6AqIov3Y/oHR 2KYkzS0zA8qic9tDkZfOMqmIMsxGQAXba0PykfChJldHlsXdz2cuiZwT0RbUWjgoR+ gFxbQg5nQw3Xv0dQPG0dm2k9R0Z72m68wY9p3kbFOz7VxPfiXWdDtnDCtUaFyF1z/l u1CPUJz+NI8OUqUx0U2fS/jewk5xeN5c5HW3SWb5BV4QKpk2B8BrDJ3ZPYwE/IahrH JszxP08gG9FgQ== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra clk_out_1, clk_out_2, and clk_out_3 are part of PMC block and these clocks are moved from clock drvier to pmc driver with pmc as a provider for these clocks. Update bindings document to use pmc as clock provider for clk_out_2 and change id to pmc clock id. Reviewed-by: Dmitry Osipenko Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni Acked-by: Thierry Reding --- Documentation/devicetree/bindings/sound/nau8825.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sound/nau8825.txt b/Documentation/devicetree/bindings/sound/nau8825.txt index d16d96839bcb..388a7bc60b1f 100644 --- a/Documentation/devicetree/bindings/sound/nau8825.txt +++ b/Documentation/devicetree/bindings/sound/nau8825.txt @@ -101,5 +101,5 @@ Example: nuvoton,crosstalk-enable; clock-names = "mclk"; - clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>; + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>; };