From patchwork Tue Jan 14 07:24:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11331443 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8BA72139A for ; Tue, 14 Jan 2020 07:26:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5583E2187F for ; Tue, 14 Jan 2020 07:26:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="cZyTnRdV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729197AbgANH0J (ORCPT ); Tue, 14 Jan 2020 02:26:09 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:13210 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728868AbgANHYe (ORCPT ); Tue, 14 Jan 2020 02:24:34 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 13 Jan 2020 23:23:38 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 13 Jan 2020 23:24:32 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 13 Jan 2020 23:24:32 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 14 Jan 2020 07:24:32 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 14 Jan 2020 07:24:32 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.169.242]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 13 Jan 2020 23:24:32 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v8 05/22] clk: tegra: Remove CLK_M_DIV fixed clocks Date: Mon, 13 Jan 2020 23:24:10 -0800 Message-ID: <1578986667-16041-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578986667-16041-1-git-send-email-skomatineni@nvidia.com> References: <1578986667-16041-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578986618; bh=LZt2qcr7rZ2Ar2X24wKYTPpid7dlgPFIqTcC62PjSPU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=cZyTnRdVoGYs27FGHv3CIBAvEYnCyKcDG7x+XWEoiSdYFC2laBIfV8jHWR/aauPNk GfT5oP0Bz/DFLSsSdRCiiVaZ5tU4w/jbTbMTPMeQoTFxFNXzU3wnYYHV2I0EfbxahA 1shvFWwZeOwP1zj+7NC4UjVgJR49vAx/8wBjPEdF8ykeZp1xPXQklm1q0It9+2Zbft SfxnhaMnF/D0+CCySA2DcGG45DmyYBVVCRsAnMqGv0NOksgmaauE2Olhzgi/2S7MUy BXsX9EEO4VjG+/o0CECdB8N6GBYjtNhfJKd1+JcoYivJGFwtVvgLvdEnOTYs2GH73z segXI1VcJN6eQ== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible parents of PMC clocks for Tegra30 through Tegra210. Tegra PMC clock parents are changed to use OSC_DIV clocks. So, this patch removes CLK_M_DIV fixed clocks Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-id.h | 2 -- drivers/clk/tegra/clk-tegra-fixed.c | 16 ---------------- drivers/clk/tegra/clk-tegra114.c | 15 --------------- drivers/clk/tegra/clk-tegra124.c | 4 ---- drivers/clk/tegra/clk-tegra210.c | 4 ---- drivers/clk/tegra/clk-tegra30.c | 4 ---- 6 files changed, 45 deletions(-) diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index 17c13d1aa6bc..cf42e5995794 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -44,8 +44,6 @@ enum clk_id { tegra_clk_clk72Mhz, tegra_clk_clk72Mhz_8, tegra_clk_clk_m, - tegra_clk_clk_m_div2, - tegra_clk_clk_m_div4, tegra_clk_osc, tegra_clk_osc_div2, tegra_clk_osc_div4, diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index 0dc2d5f5cfb5..77c22cef5014 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -105,22 +105,6 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768); *dt_clk = clk; } - - /* clk_m_div2 */ - dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks); - if (dt_clk) { - clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", - CLK_SET_RATE_PARENT, 1, 2); - *dt_clk = clk; - } - - /* clk_m_div4 */ - dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks); - if (dt_clk) { - clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", - CLK_SET_RATE_PARENT, 1, 4); - *dt_clk = clk; - } } void tegra_clk_osc_resume(void __iomem *clk_base) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index e3c68eca54b7..180ddc2abfd2 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -735,8 +735,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true }, [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true }, [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true }, - [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true }, - [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true }, [tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true }, [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true }, [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true }, @@ -818,8 +816,6 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M }, { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF }, { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K }, - { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 }, - { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 }, { .con_id = "osc", .dt_id = TEGRA114_CLK_OSC }, { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 }, { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 }, @@ -906,17 +902,6 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base) /* clk_32k */ clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768); clks[TEGRA114_CLK_CLK_32K] = clk; - - /* clk_m_div2 */ - clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", - CLK_SET_RATE_PARENT, 1, 2); - clks[TEGRA114_CLK_CLK_M_DIV2] = clk; - - /* clk_m_div4 */ - clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", - CLK_SET_RATE_PARENT, 1, 4); - clks[TEGRA114_CLK_CLK_M_DIV4] = clk; - } static void __init tegra114_pll_init(void __iomem *clk_base, diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index ef0f928f0259..7a16e50eb20f 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -860,8 +860,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true }, [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true }, [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true }, - [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true }, - [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true }, [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true }, [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true }, [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true }, @@ -944,8 +942,6 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M }, { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF }, { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K }, - { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 }, - { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 }, { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC }, { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 }, { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 }, diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 958f5f6c894d..45d54ead30bc 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2371,8 +2371,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true }, [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true }, [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true }, - [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true }, - [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true }, [tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true }, [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true }, [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true }, @@ -2500,8 +2498,6 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M }, { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF }, { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K }, - { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 }, - { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 }, { .con_id = "osc", .dt_id = TEGRA210_CLK_OSC }, { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 }, { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 }, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 5f3484758123..ddc5ab66d09e 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -581,8 +581,6 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD }, { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC }, { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K }, - { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 }, - { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 }, { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC }, { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 }, { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 }, @@ -686,8 +684,6 @@ static struct tegra_devclk devclks[] __initdata = { static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true }, [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true }, - [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true }, - [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true }, [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true }, [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true }, [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },