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Tue, 28 Jan 2020 05:28:32 +0000 From: Peng Fan To: "sboyd@kernel.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "festevam@gmail.com" , Abel Vesa , Leonard Crestez CC: "kernel@pengutronix.de" , dl-linux-imx , Aisheng Dong , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anson Huang , Jacky Bai , "l.stach@pengutronix.de" , Peng Fan Subject: [PATCH V4 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite_core Thread-Topic: [PATCH V4 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite_core Thread-Index: AQHV1ZvKDxq3UpFxMEyFV9hEtp7TTw== Date: Tue, 28 Jan 2020 05:28:36 +0000 Message-ID: <1580189015-5744-2-git-send-email-peng.fan@nxp.com> References: <1580189015-5744-1-git-send-email-peng.fan@nxp.com> In-Reply-To: <1580189015-5744-1-git-send-email-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0113.apcprd03.prod.outlook.com (2603:1096:203:b0::29) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; 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x-microsoft-antispam-message-info: hp9H5PyO5Nv42ftq7ZcRvqq5A74BQ4h0S+fhMwseNB+RqdH2ZUK5da8ArQ9COfHBqv/MPqrr2TpXt/FZQ6KAJKPMRJpBh1+nUp392ryEFThR7THOqaeF5kcr4/qy30ZwbvczvexEV3DhTOqb5jy9JUWt5eVfEEWXV4CU6OtvDQLO56PbguF/ofFaHpEhldgVvQspvmyfvNJAJo8EevP8HYNHtZiJSMjT+ZIm9M3ybUKDDu4ueG6LCKh8CPMFChrfOM2qDJbDb4qbvtAJoTS5XP3CstQ0oOlXsDQG/jylq/0J3fgluJNxwgZ8d4ape+GIXdm21xllyqD/kwLNhtJv/mZ+1EFhl6fPpJjFtEqV5VGR5ApNcMda6/JIzAq+JDWI79kGZY7IKdXX54MpKrNQEALnbvs3nxTJYIdIgRXn3Pf1WeVMnQw6EI+yxraP74V36vOahRrz1dJj6deVyGQ76Ou0Vb43flYHvFkk5LP+pnT2F4TFyaqBVJzvexX+7Pmv9sLhLlsEBTIRORgl0JWvOX9nkE1PDJfNiKtRms/1nYA= x-ms-exchange-antispam-messagedata: QFeah0X2Fc6NwW0jMZlZVpxeUllN6RtuUp+w1u7Cs9fILZUAkQTHipmxWwlyyxZob1nLEvAm8L9fmnMx/sEEEj5dR3HM0jmSiiHQNT1AXQT8Lttmb8Gf4iIywErs8t7K619Rlm8W7kMbxVYQrSmNNg== MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c51b3319-ea4d-4768-30d1-08d7a3b2eca9 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jan 2020 05:28:36.8312 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TE+6gdJb+4v8mGQcEB0XN3XYXBhe557OHGo7hDgGPPvLxfVzDyBXGVubwhWWPMZNcSCkDAlMzfCQsSBahapKRQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB5890 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan There are several clock slices, current composite code only support bus/ip clock slices, it could not support core slice. So introduce a new API imx8m_clk_hw_composite_core to support core slice. To core slice, post divider with 3 bits width and no pre divider. Other fields are same as bus/ip slices. Add a flag IMX_COMPOSITE_CORE for the usecase. Reviewed-by: Abel Vesa Signed-off-by: Peng Fan --- drivers/clk/imx/clk-composite-8m.c | 18 ++++++++++++++---- drivers/clk/imx/clk.h | 13 +++++++++++-- 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index 20f7c91c03d2..4869c16376bf 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -15,6 +15,7 @@ #define PCG_PREDIV_MAX 8 #define PCG_DIV_SHIFT 0 +#define PCG_CORE_DIV_WIDTH 3 #define PCG_DIV_WIDTH 6 #define PCG_DIV_MAX 64 @@ -126,6 +127,7 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = { struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, + u32 composite_flags, unsigned long flags) { struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; @@ -133,6 +135,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, struct clk_divider *div = NULL; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; + const struct clk_ops *divider_ops; mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) @@ -150,8 +153,16 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, div_hw = &div->hw; div->reg = reg; - div->shift = PCG_PREDIV_SHIFT; - div->width = PCG_PREDIV_WIDTH; + if (composite_flags & IMX_COMPOSITE_CORE) { + div->shift = PCG_DIV_SHIFT; + div->width = PCG_CORE_DIV_WIDTH; + divider_ops = &clk_divider_ops; + } else { + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + divider_ops = &imx8m_clk_composite_divider_ops; + } + div->lock = &imx_ccm_lock; div->flags = CLK_DIVIDER_ROUND_CLOSEST; @@ -166,8 +177,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ops, div_hw, - &imx8m_clk_composite_divider_ops, - gate_hw, &clk_gate_ops, flags); + divider_ops, gate_hw, &clk_gate_ops, flags); if (IS_ERR(hw)) goto fail; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index b05213b91dcf..f074dd8ec42e 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +#define IMX_COMPOSITE_CORE BIT(0) + struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, + u32 composite_flags, unsigned long flags); +#define imx8m_clk_hw_composite_core(name, parent_names, reg) \ + imx8m_clk_hw_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, \ + IMX_COMPOSITE_CORE, \ + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \ flags) \ to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \ - num_parents, reg, flags)) + num_parents, reg, 0, flags)) #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \ imx8m_clk_hw_composite_flags(name, parent_names, \ - ARRAY_SIZE(parent_names), reg, \ + ARRAY_SIZE(parent_names), reg, 0, \ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) #define __imx8m_clk_composite(name, parent_names, reg, flags) \