Message ID | 1580823277-13644-7-git-send-email-peng.fan@nxp.com (mailing list archive) |
---|---|
State | Changes Requested, archived |
Headers | show |
Series | [1/7] clk: imx: Fix division by zero warning on pfdv2 | expand |
Hi Peng, On Tue, Feb 4, 2020 at 10:41 AM <peng.fan@nxp.com> wrote: > > From: Peng Fan <peng.fan@nxp.com> > > Configure pmprot to let ARM core could run into HSRUN mode. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > + writel_relaxed(BM_PMPROT_AHSRUN, smc1_base + SMC_PMPROT); HSRUN cannot be configured unconditionally because if i.MX7ULP runs with LDO-enabled it cannot run in HSRUN mode.
> Subject: Re: [PATCH 6/7] ARM: imx: imx7ulp: support HSRUN mode > > Hi Peng, > > On Tue, Feb 4, 2020 at 10:41 AM <peng.fan@nxp.com> wrote: > > > > From: Peng Fan <peng.fan@nxp.com> > > > > Configure pmprot to let ARM core could run into HSRUN mode. > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > > + writel_relaxed(BM_PMPROT_AHSRUN, smc1_base + > SMC_PMPROT); > > HSRUN cannot be configured unconditionally because if i.MX7ULP runs with > LDO-enabled it cannot run in HSRUN mode. Thanks, I'll update to add a check LDO mode here. Thanks, Peng.
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c index 7b2f7387e662..dc2bc6f2cadd 100644 --- a/arch/arm/mach-imx/pm-imx7ulp.c +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -11,6 +11,7 @@ #include "common.h" +#define SMC_PMPROT 0x8 #define SMC_PMCTRL 0x10 #define BP_PMCTRL_PSTOPO 16 #define PSTOPO_PSTOP3 0x3 @@ -25,6 +26,8 @@ #define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM) #define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM) +#define BM_PMPROT_AHSRUN BIT(7) + static void __iomem *smc1_base; int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) @@ -51,6 +54,7 @@ int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) return -EINVAL; } + writel_relaxed(BM_PMPROT_AHSRUN, smc1_base + SMC_PMPROT); writel_relaxed(val, smc1_base + SMC_PMCTRL); return 0;