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Wed, 19 Feb 2020 09:59:44 +0000 From: peng.fan@nxp.com To: sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, abel.vesa@nxp.com, leonard.crestez@nxp.com Cc: kernel@pengutronix.de, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anson.huang@nxp.com, ping.bai@nxp.com, l.stach@pengutronix.de, Peng Fan Subject: [PATCH V3 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite_core Date: Wed, 19 Feb 2020 17:53:35 +0800 Message-Id: <1582106022-20926-2-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> References: <1582106022-20926-1-git-send-email-peng.fan@nxp.com> X-ClientProxiedBy: HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) MIME-Version: 1.0 Received: from localhost.localdomain (119.31.174.66) by HK2PR0302CA0008.apcprd03.prod.outlook.com (2603:1096:202::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2750.8 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: oCdmfLr0Aief1Inn9DCOPo+7qIe7aoaUGVM6hdAzjlviQpOk59oVxmcbgm/7Q6hJauA9wBzdSdy4izaU90gI+kYjBne2XH3nEikaxbFYi1lyzyvQfo8ORY04POzd3YlHF06YQBJyelZufFU56l50ljHb+zj8Rc7452NrZWyu/a7nCYrkzkCKRdsKZdkzxv1pJzcvRHo3YOh6grjV1Tbf+cZL9csXL9AHN6YaBgKiyRhf0i/1N3F3JR0R73qNax/jLbRzRpe6ZDHkT9p9LYMs0lyDwQpeJUVr+m5opJehPEeZ8pJMBI8mUW4FcUtBc/1chRHtI+fZiH3oWBMdoP4Biez3cebgIG3K7PBwa9kvb4vvVpPaE7EArqgODvdS7Vg/LmnRqO81hB9S+VJ+/9Ssva5wdMfFVhPHI07x6wO69T/PPLwVsDFGdyLCE27+Oen6oodfU4iypCsHn3Oa2VLx67KDPegYZfG0iuronI0D4FcxkG/n27GruN8rjSwNgwnZ30KCBVx3XxfgbdUQwWAfjwYQqYvLWyWKKaWnNZqAR94= X-MS-Exchange-AntiSpam-MessageData: nkOpPJIvAfYqHMOa4Sur1x5wHhkw8+bk1B1hvQCTRK+NOMwd+UJkhWVUAO1uvkhTewVaRoEGJEX5ullLfDp6Pn7DUBkplCeA7VdDAPpKWqcSz8MtTRMCj6jQ2hNPA0pwnqx7lvvrvO9aHphU8/oYSw== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: eb7bbb8d-db4a-4070-c23a-08d7b52271e0 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Feb 2020 09:59:44.2164 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: tuR5FiYSqmbIDK9/QtPWm3mmDOroa4zUOlfqU4FtPmtvRXQP8dYV5dd8zzEJ8JgEP/fVTOK4CFUzD304TKcwcg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6514 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan There are several clock slices, current composite code only support bus/ip clock slices, it could not support core slice. So introduce a new API imx8m_clk_hw_composite_core to support core slice. To core slice, post divider with 3 bits width and no pre divider. Other fields are same as bus/ip slices. Add a flag IMX_COMPOSITE_CORE for the usecase. Reviewed-by: Abel Vesa Signed-off-by: Peng Fan --- drivers/clk/imx/clk-composite-8m.c | 18 ++++++++++++++---- drivers/clk/imx/clk.h | 13 +++++++++++-- 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index e0f25983e80f..4174506e8bdd 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -15,6 +15,7 @@ #define PCG_PREDIV_MAX 8 #define PCG_DIV_SHIFT 0 +#define PCG_CORE_DIV_WIDTH 3 #define PCG_DIV_WIDTH 6 #define PCG_DIV_MAX 64 @@ -126,6 +127,7 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = { struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, + u32 composite_flags, unsigned long flags) { struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; @@ -133,6 +135,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, struct clk_divider *div = NULL; struct clk_gate *gate = NULL; struct clk_mux *mux = NULL; + const struct clk_ops *divider_ops; mux = kzalloc(sizeof(*mux), GFP_KERNEL); if (!mux) @@ -149,8 +152,16 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, div_hw = &div->hw; div->reg = reg; - div->shift = PCG_PREDIV_SHIFT; - div->width = PCG_PREDIV_WIDTH; + if (composite_flags & IMX_COMPOSITE_CORE) { + div->shift = PCG_DIV_SHIFT; + div->width = PCG_CORE_DIV_WIDTH; + divider_ops = &clk_divider_ops; + } else { + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + divider_ops = &imx8m_clk_composite_divider_ops; + } + div->lock = &imx_ccm_lock; div->flags = CLK_DIVIDER_ROUND_CLOSEST; @@ -164,8 +175,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ops, div_hw, - &imx8m_clk_composite_divider_ops, - gate_hw, &clk_gate_ops, flags); + divider_ops, gate_hw, &clk_gate_ops, flags); if (IS_ERR(hw)) goto fail; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index b05213b91dcf..f074dd8ec42e 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +#define IMX_COMPOSITE_CORE BIT(0) + struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, + u32 composite_flags, unsigned long flags); +#define imx8m_clk_hw_composite_core(name, parent_names, reg) \ + imx8m_clk_hw_composite_flags(name, parent_names, \ + ARRAY_SIZE(parent_names), reg, \ + IMX_COMPOSITE_CORE, \ + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \ flags) \ to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \ - num_parents, reg, flags)) + num_parents, reg, 0, flags)) #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \ imx8m_clk_hw_composite_flags(name, parent_names, \ - ARRAY_SIZE(parent_names), reg, \ + ARRAY_SIZE(parent_names), reg, 0, \ flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) #define __imx8m_clk_composite(name, parent_names, reg, flags) \