From patchwork Fri Feb 21 10:12:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 11396025 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E553E14E3 for ; Fri, 21 Feb 2020 10:12:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BACD220722 for ; Fri, 21 Feb 2020 10:12:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ZjpbilcP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728679AbgBUKMU (ORCPT ); Fri, 21 Feb 2020 05:12:20 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:43041 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728486AbgBUKMU (ORCPT ); Fri, 21 Feb 2020 05:12:20 -0500 X-UUID: 0c24167ae63b4e46ad5a75006e3580ab-20200221 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=lyh07rORdyEMmH4qVkXFosUAcAB4Aohej6iysxVm6AY=; b=ZjpbilcPr35xQ4wjjfxsL615+NKCKhoTD4WTehZAfkPD8f65gZFh7cdFNmPIFk0ll1rZf12beMDuZjH1sj9M9nILDdSSgJYlZ7/IltVBVgMshh9JwXPdg9BBh/njxwi+k9/a5XxEfXCkqVmH4ZBHySe+piTOuaMsAVvCuPfQ7qA=; X-UUID: 0c24167ae63b4e46ad5a75006e3580ab-20200221 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1107465619; Fri, 21 Feb 2020 18:12:13 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 21 Feb 2020 18:13:16 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 21 Feb 2020 18:11:53 +0800 From: Macpaul Lin To: Rob Herring , Mark Rutland , Matthias Brugger , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , mtk01761 , Fabien Parent , Weiyi Lu , Mars Cheng , Sean Wang , Macpaul Lin , Owen Chen , Chunfeng Yun , Evan Green , Yong Wu , Joerg Roedel , Shawn Guo , Marc Zyngier , Ryder Lee , , , , , CC: Mediatek WSD Upstream , CC Hwang , Loda Chou Subject: [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support Date: Fri, 21 Feb 2020 18:12:07 +0800 Message-ID: <1582279929-11535-3-git-send-email-macpaul.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1582279929-11535-1-git-send-email-macpaul.lin@mediatek.com> References: <1582279929-11535-1-git-send-email-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Mars Cheng This adds scpsys support for MT6765 Add subdomain support for MT6765: isp, mm, connsys, mfg, and cam. Signed-off-by: Mars Cheng Signed-off-by: Owen Chen Signed-off-by: Macpaul Lin --- drivers/soc/mediatek/mtk-scpsys.c | 130 +++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index f669d37..9940c6d 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -750,6 +751,120 @@ static void mtk_register_power_domains(struct platform_device *pdev, }; /* + * MT6765 power domain support + */ +#define SPM_PWR_STATUS_MT6765 0x0180 +#define SPM_PWR_STATUS_2ND_MT6765 0x0184 + +static const struct scp_domain_data scp_domain_data_mt6765[] = { + [MT6765_POWER_DOMAIN_VCODEC] = { + .name = "vcodec", + .sta_mask = BIT(26), + .ctl_offs = 0x300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT6765_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = BIT(5), + .ctl_offs = 0x308, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .subsys_clk_prefix = "isp", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, + BIT(20), BIT(20)), + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, + BIT(2), BIT(2)), + }, + }, + [MT6765_POWER_DOMAIN_MM] = { + .name = "mm", + .sta_mask = BIT(3), + .ctl_offs = 0x30C, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_id = {"mm"}, + .subsys_clk_prefix = "mm", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, + BIT(16) | BIT(17), BIT(16) | BIT(17)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(10) | BIT(11), BIT(10) | BIT(11)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(1) | BIT(2), BIT(1) | BIT(2)), + }, + }, + [MT6765_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = BIT(1), + .ctl_offs = 0x32C, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(13), BIT(13)), + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, + BIT(18), BIT(18)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(14) | BIT(16), BIT(14) | BIT(16)), + }, + }, + [MT6765_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = BIT(23), + .ctl_offs = 0x334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .basic_clk_id = {"mfg"}, + }, + [MT6765_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = BIT(4), + .ctl_offs = 0x338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(25), BIT(25)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(21) | BIT(22), BIT(21) | BIT(22)), + } + }, + [MT6765_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x344, + .sram_pdn_bits = GENMASK(8, 9), + .sram_pdn_ack_bits = GENMASK(12, 13), + .subsys_clk_prefix = "cam", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, + BIT(19) | BIT(21), BIT(19) | BIT(21)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(20), BIT(20)), + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, + BIT(3), BIT(3)), + } + }, + [MT6765_POWER_DOMAIN_MFG_CORE0] = { + .name = "mfg_core0", + .sta_mask = BIT(7), + .ctl_offs = 0x34C, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, +}; + +static const struct scp_subdomain scp_subdomain_mt6765[] = { + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM}, + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP}, + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC}, + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG}, + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0}, +}; + +/* * MT6797 power domain support */ @@ -1032,6 +1147,18 @@ static void mtk_register_power_domains(struct platform_device *pdev, .bus_prot_reg_update = false, }; +static const struct scp_soc_data mt6765_data = { + .domains = scp_domain_data_mt6765, + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765), + .subdomains = scp_subdomain_mt6765, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765), + .regs = { + .pwr_sta_offs = SPM_PWR_STATUS_MT6765, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765, + }, + .bus_prot_reg_update = true, +}; + static const struct scp_soc_data mt6797_data = { .domains = scp_domain_data_mt6797, .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), @@ -1088,6 +1215,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, .compatible = "mediatek,mt2712-scpsys", .data = &mt2712_data, }, { + .compatible = "mediatek,mt6765-scpsys", + .data = &mt6765_data, + }, { .compatible = "mediatek,mt6797-scpsys", .data = &mt6797_data, }, {