From patchwork Sun Mar 15 01:46:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11438509 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA0741392 for ; Sun, 15 Mar 2020 01:46:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AA05220773 for ; Sun, 15 Mar 2020 01:46:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="FP5fo5CU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727352AbgCOBqh (ORCPT ); Sat, 14 Mar 2020 21:46:37 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18901 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727286AbgCOBqH (ORCPT ); Sat, 14 Mar 2020 21:46:07 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sat, 14 Mar 2020 18:45:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 14 Mar 2020 18:46:06 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 14 Mar 2020 18:46:06 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 15 Mar 2020 01:46:06 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 15 Mar 2020 01:46:06 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.141]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sat, 14 Mar 2020 18:46:06 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , Subject: [RFC PATCH v4 4/8] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Sat, 14 Mar 2020 18:46:02 -0700 Message-ID: <1584236766-24819-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584236766-24819-1-git-send-email-skomatineni@nvidia.com> References: <1584236766-24819-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584236753; bh=OGs3CNdnpPztJ28S1nwc0JHJg2nXou6ljJssqTIUQtQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=FP5fo5CUWv4SgzwBXS2D4SA+W43XrhZ5UAGEp07qi+qNfIY8qoz1uXC5vJ6gsmnGl DcIOklYcdGBRRDc6wrcVKuPdOyQviaolb8KkqIPw8+QbNHUEwm4pn1vsXI25HF2zOP L/WZZbN1f8oKBK0uU9OKxgPzeEVZ6GMlYzYvkVYbPhIij+BgLn0EwGonOCXT4ZxD9t z+3uVqyHah3mTRvFL4NGaGEz1cIqgCSAsu7und/+Jel+Jy2xPn7TvVImp2oL5uC0sk 27L7NDG4jXQsCOglf0/816gAH4IlinFMK6JvQ0bmQqEwhv8UExDmON+lkegvBGepG3 NunsBSPbYEqXg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index c6304f5..58a67c7 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d_out0", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base,