| Message ID | 1584236766-24819-9-git-send-email-skomatineni@nvidia.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [RFC,v4,1/8] arm64: tegra: Fix sor powergate clocks and reset | expand |
15.03.2020 04:46, Sowjanya Komatineni пишет: > Tegra210 contains VI controller for video input capture from MIPI > CSI camera sensors and also supports built-in test pattern generator. > > CSI ports can be one-to-one mapped to VI channels for capturing from > an external sensor or from built-in test pattern generator. > > This patch adds support for VI and CSI and enables them in Tegra210 > device tree. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- Hello Sowjanya, ... > + > + pd_venc: venc { > + clocks = <&tegra_car TEGRA210_CLK_VI>, > + <&tegra_car TEGRA210_CLK_CSI>; > + resets = <&tegra_car 20>, What is the clock #20? > + <&tegra_car TEGRA210_CLK_CSI>, > + <&mc TEGRA210_MC_RESET_VI>; Does this order means that memory controller will be reset *after* resetting the CSI/VI hardware? This is incorrect reset sequence. The memory controller reset should be kept asserted during of the time of the hardware resetting procedure. The correct sequence should be as follows: 1. Assert MC 2. Reset VI 3. Deassert MC
On 3/15/20 5:54 AM, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments > > > 15.03.2020 04:46, Sowjanya Komatineni пишет: >> Tegra210 contains VI controller for video input capture from MIPI >> CSI camera sensors and also supports built-in test pattern generator. >> >> CSI ports can be one-to-one mapped to VI channels for capturing from >> an external sensor or from built-in test pattern generator. >> >> This patch adds support for VI and CSI and enables them in Tegra210 >> device tree. >> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >> --- > Hello Sowjanya, > > ... >> + >> + pd_venc: venc { >> + clocks = <&tegra_car TEGRA210_CLK_VI>, >> + <&tegra_car TEGRA210_CLK_CSI>; >> + resets = <&tegra_car 20>, > What is the clock #20? Hi Dmitry, 20 is VI_RST not defined in include/dt-bindings/reset/tegra210-car.h Will add define and will fix to use it. >> + <&tegra_car TEGRA210_CLK_CSI>, >> + <&mc TEGRA210_MC_RESET_VI>; > Does this order means that memory controller will be reset *after* > resetting the CSI/VI hardware? This is incorrect reset sequence. > > The memory controller reset should be kept asserted during of the time > of the hardware resetting procedure. > > The correct sequence should be as follows: > > 1. Assert MC > 2. Reset VI > 3. Deassert MC Right, will fix order. Thanks
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 313a4c2..b57d837 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 5b1dfd8..14d292b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -137,9 +137,43 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + clock-names = "vi"; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>; + clock-names = "csi", "cilab", "cilcd", "cile"; + power-domains = <&pd_sor>; + }; + }; tsec@54100000 { @@ -839,6 +873,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&tegra_car 20>, + <&tegra_car TEGRA210_CLK_CSI>, + <&mc TEGRA210_MC_RESET_VI>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 {
Tegra210 contains VI controller for video input capture from MIPI CSI camera sensors and also supports built-in test pattern generator. CSI ports can be one-to-one mapped to VI channels for capturing from an external sensor or from built-in test pattern generator. This patch adds support for VI and CSI and enables them in Tegra210 device tree. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 10 ++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 45 +++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-)