From patchwork Wed Apr 22 06:18:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11502961 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E14615AB for ; Wed, 22 Apr 2020 06:19:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7C630206CD for ; Wed, 22 Apr 2020 06:19:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="cXLWDk0n" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726447AbgDVGTG (ORCPT ); Wed, 22 Apr 2020 02:19:06 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:3216 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726415AbgDVGTD (ORCPT ); Wed, 22 Apr 2020 02:19:03 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 21 Apr 2020 23:18:01 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 21 Apr 2020 23:19:03 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 21 Apr 2020 23:19:03 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 22 Apr 2020 06:19:03 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 22 Apr 2020 06:19:03 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 21 Apr 2020 23:19:03 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v9 2/9] arm64: tegra: Add reset-cells to mc Date: Tue, 21 Apr 2020 23:18:52 -0700 Message-ID: <1587536339-4030-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587536339-4030-1-git-send-email-skomatineni@nvidia.com> References: <1587536339-4030-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587536281; bh=fypsljnYXUQBk09pkBuzFp0S2nxT0B9eauugx/SlCBI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=cXLWDk0n9myOrDy67vaDWZGWBQG/Wb/b9U1B5QY+Wmct48uDNcQwQpcbQ4BqPzcGV F0T3hDJ65DqRNaERaJJUbLW5q9t7sdfM6E3U7b6rB3qujediOu3lncrGvYZPkrh2jz PIi8RQkwE98EOaXPZO6jKreKw2+o+1CE/sJszqcOI2K1bQMmnphCTniUjTKdsvizdT LS5dle/7yknomnAMUbh9YNivvTwVdxHa7vAx3cj3oS3g2QYpqVCtvU4/p6dJGxhNey fdW72xqDEYspwty9Trjm5/6A4HWt6IdIQpYwbCQaku/JDVXgjeMUBWMCd3p+69F8RI 8f9o4o2XPHxTg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 device tree is missing reset-cells property for mc node. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index d0eff92..5b1dfd8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -894,6 +894,7 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; }; sata@70020000 {