From patchwork Wed Apr 22 06:18:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11502969 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1463D1667 for ; Wed, 22 Apr 2020 06:19:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F081E2070B for ; Wed, 22 Apr 2020 06:19:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="O0clgWuG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726611AbgDVGTk (ORCPT ); Wed, 22 Apr 2020 02:19:40 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:15628 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726437AbgDVGTF (ORCPT ); Wed, 22 Apr 2020 02:19:05 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 21 Apr 2020 23:17:09 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 21 Apr 2020 23:19:05 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 21 Apr 2020 23:19:05 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 22 Apr 2020 06:19:04 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 22 Apr 2020 06:19:04 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.49]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 21 Apr 2020 23:19:04 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v9 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Tue, 21 Apr 2020 23:18:54 -0700 Message-ID: <1587536339-4030-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587536339-4030-1-git-send-email-skomatineni@nvidia.com> References: <1587536339-4030-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587536229; bh=/06MYnopqzjyrf2N0nRAUhGBnkcd6r/kBjlHyehzo9I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=O0clgWuGB6/asspJt9RbOj381NpF1O/iIXKgfoNNjGpkClaO6/prJ/Huu9nBBVAYP OepJl1LRqHtabFS7p4eQ+VHRihswx7HRpdTgCdMCYunGH03YUcpqKWu6fzPbdIz0/T cw2U7znBVWaJFJ5N/CD6p1riCruH18J0b0jHXw71AJv6lg5gQlTzIwXt1X7VRmsh55 wg+DdE3Nv678ymjrigUU5gYsDvxA84RPJtQbMDP7ndg57oAyVdZs4F+eMQeBVd33Rg yToZcMF9cTn9IH70enmbTEw8bws9wKjQTmSDee88uaY0g9Z6ArTqSD/t3UfyjcRvry Mm2ZdXnmma09g== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index defe3b7..81a879b 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base,