From patchwork Tue May 5 02:31:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11528079 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1118214C0 for ; Tue, 5 May 2020 02:31:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id ED42720735 for ; Tue, 5 May 2020 02:31:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="FJWW8qJA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728455AbgEECbm (ORCPT ); Mon, 4 May 2020 22:31:42 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:13708 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727805AbgEECbI (ORCPT ); Mon, 4 May 2020 22:31:08 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 04 May 2020 19:28:58 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 04 May 2020 19:31:06 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 04 May 2020 19:31:06 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 5 May 2020 02:31:06 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 5 May 2020 02:31:06 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.165.119]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 04 May 2020 19:31:06 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , , , Subject: [RFC PATCH v12 4/9] clk: tegra: Add Tegra210 CSI TPG clock gate Date: Mon, 4 May 2020 19:31:55 -0700 Message-ID: <1588645920-20557-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588645920-20557-1-git-send-email-skomatineni@nvidia.com> References: <1588645920-20557-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1588645738; bh=OkPuoK2fo6rVufUctg2RvCrQeMtaLrjub70xyZxzmrU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=FJWW8qJAI6RCUAlpB1soV9Vx39P1+m4Z+J7bpYY4duHANp03Te0TMor/rt4WNRCOu UpRA1x62dWAKB3guH8aIVGeGtH3WZ1O+zREkuSfnE5ve3wNczp1jvEA4bYBt5wlUps 6NdzsXZY/jossIk4GzFtU2GxE5jJw/DrokfpqD8jL6xt5kkXCR6NqHYNTRiVg0NFN7 ULihq1C4o91Brnv4Oc0Jp+cFF3bNjKFBiCnmOj4Wb5yCfWnyO7E9KNOkLL+/251phF Re2ur3fcMeorW3EgC6MXlrHA6uGdKH5IsHV2c1eYi0d3HYTHD4OSUWSJd1z8f0068l mpwoAL0dWPqLg== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd Signed-off-by: Sowjanya Komatineni --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index f2bb188..68cbb98 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3076,6 +3076,13 @@ static __init void tegra210_periph_clk_init(struct device_node *np, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base,