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Mon, 1 Jun 2020 03:53:55 +0000 From: peng.fan@nxp.com To: shawnguo@kernel.org, fabio.estevam@nxp.com, kernel@pengutronix.de, aisheng.dong@nxp.com, robh+dt@kernel.org, sboyd@kernel.org, linux@rempel-privat.de, jaswinder.singh@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-imx@nxp.com, leonard.crestez@nxp.com, daniel.baluta@nxp.com, l.stach@pengutronix.de, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Peng Fan Subject: [PATCH V2 2/3] arm64: dts: imx8m: add mu node Date: Mon, 1 Jun 2020 11:43:18 +0800 Message-Id: <1590982999-7149-3-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590982999-7149-1-git-send-email-peng.fan@nxp.com> References: <1590982999-7149-1-git-send-email-peng.fan@nxp.com> X-ClientProxiedBy: SG2PR03CA0096.apcprd03.prod.outlook.com (2603:1096:4:7c::24) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0096.apcprd03.prod.outlook.com (2603:1096:4:7c::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3066.7 via Frontend Transport; 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Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++ 4 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index aaf6e71101a1..fc001fb971e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -775,6 +775,15 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 9a4b65a267d4..c8290d21ccc9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -675,6 +675,15 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 45e2c0a4e889..b530804f763e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -621,6 +621,15 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + i2c5: i2c@30ad0000 { compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 978f8122c0d2..66ba8da704f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -959,6 +959,15 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_MU_ROOT>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";