From patchwork Thu Jun 18 11:33:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanks Chen X-Patchwork-Id: 11611857 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A2F89912 for ; Thu, 18 Jun 2020 11:34:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8AF182071A for ; Thu, 18 Jun 2020 11:34:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="PrQaosCs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729514AbgFRLeR (ORCPT ); Thu, 18 Jun 2020 07:34:17 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:51063 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728048AbgFRLeJ (ORCPT ); Thu, 18 Jun 2020 07:34:09 -0400 X-UUID: a94d3c64965642309da38fbdceb20e6d-20200618 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=x+yhsVMil1EiA17Zrkn38qhTWyswuL0rzxglJr9tsjs=; b=PrQaosCsZeCJZl2fPa+JeyC6d+L5mMAI+dJfg1g2qPIOXYo19aR7rScmT0GG5UaajWPRcCh7vhIF1ESCY54En6kxpaMXNRzZ3c80uZi/i+ldha4abDDYTIJ0WzLxZuG9u8AWBSgLeDMD7IAciourQWaEV7N3kLG2dcxqeWVsjCY=; X-UUID: a94d3c64965642309da38fbdceb20e6d-20200618 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 676282247; Thu, 18 Jun 2020 19:34:06 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 18 Jun 2020 19:34:01 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Jun 2020 19:34:02 +0800 From: Hanks Chen To: Linus Walleij , Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd , Sean Wang CC: mtk01761 , Andy Teng , , , , , , , , CC Hwang , Loda Chou , Hanks Chen Subject: [PATCH v6 6/7] clk: mediatek: add UART0 clock support Date: Thu, 18 Jun 2020 19:33:37 +0800 Message-ID: <1592480018-3340-7-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> References: <1592480018-3340-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: FB95E0EE193F82EDDAB6AE7DE289638071D94AEE1E98FE6F6EB8A722D1B67CE12000:8 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add MT6779 UART0 clock support. Signed-off-by: Hanks Chen Signed-off-by: mtk01761 --- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766ccc..6e0d3a1 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",