From patchwork Thu Jul 30 13:30:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanks Chen X-Patchwork-Id: 11693049 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 174CD13B6 for ; Thu, 30 Jul 2020 13:30:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F28D320829 for ; Thu, 30 Jul 2020 13:30:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tRDq7tvq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728442AbgG3Naa (ORCPT ); Thu, 30 Jul 2020 09:30:30 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:64199 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728124AbgG3Naa (ORCPT ); Thu, 30 Jul 2020 09:30:30 -0400 X-UUID: 0bb7a2cb8fa54bc79c670b81e4803f08-20200730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=bItawRI4WETjkWbsEIQmhgb5ptmHRsFuKCwxFVOHsUs=; b=tRDq7tvqsZ+6Ukc0BSZjtM64ueBBtjCJXGmw9y50K1hSSisZyX3KLs7rvzyfM06bXwTWg7A8rAyNkiQzap+68FJxIC1ewOzJaTN5YR7HHmdgTDjjcsWwiR7hp9mPdzmIw2He6wcm7BZ2nODFdAIWuAX1wQwX8PuB2CNzWjVgaY8=; X-UUID: 0bb7a2cb8fa54bc79c670b81e4803f08-20200730 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1667719543; Thu, 30 Jul 2020 21:30:26 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 30 Jul 2020 21:30:15 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 30 Jul 2020 21:30:16 +0800 From: Hanks Chen To: Linus Walleij , Rob Herring , Matthias Brugger , "Michael Turquette" , Stephen Boyd CC: mtk01761 , YueHaibing , Andy Teng , , , , , , , CC Hwang , Loda Chou , Hanks Chen Subject: [PATCH v10 3/3] clk: mediatek: add UART0 clock support Date: Thu, 30 Jul 2020 21:30:16 +0800 Message-ID: <1596115816-11758-4-git-send-email-hanks.chen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1596115816-11758-1-git-send-email-hanks.chen@mediatek.com> References: <1596115816-11758-1-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 3BA704DB6C7DA6D467F870690FBF3F154F2185A65B7A8BB18CAA73AC904410942000:8 X-MTK: N Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add MT6779 UART0 clock support. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Wendell Lin Signed-off-by: Hanks Chen Reviewed-by: Matthias Brugger --- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766cccf5844..6e0d3a166729 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",