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Thu, 10 Sep 2020 10:44:32 +0000 From: Sagar Kadam To: linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, aou@eecs.berkeley.edu, yash.shah@sifive.com, Sagar Kadam Subject: [PATCH v1 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Date: Thu, 10 Sep 2020 16:14:02 +0530 Message-Id: <1599734644-4791-2-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599734644-4791-1-git-send-email-sagar.kadam@sifive.com> References: <1599734644-4791-1-git-send-email-sagar.kadam@sifive.com> X-ClientProxiedBy: BMXPR01CA0087.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:54::27) To DM6PR13MB3451.namprd13.prod.outlook.com (2603:10b6:5:1c3::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from osubuntu003.open-silicon.com (159.117.144.156) by BMXPR01CA0087.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:54::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3326.19 via Frontend Transport; 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Signed-off-by: Sagar Kadam --- .../bindings/clock/sifive/fu540-prci.txt | 46 ------------- .../bindings/clock/sifive/fu540-prci.yaml | 75 ++++++++++++++++++++++ 2 files changed, 75 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt deleted file mode 100644 index 349808f..0000000 --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt +++ /dev/null @@ -1,46 +0,0 @@ -SiFive FU540 PRCI bindings - -On the FU540 family of SoCs, most system-wide clock and reset integration -is via the PRCI IP block. - -Required properties: -- compatible: Should be "sifive,-prci". Only one value is - supported: "sifive,fu540-c000-prci" -- reg: Should describe the PRCI's register target physical address region -- clocks: Should point to the hfclk device tree node and the rtcclk - device tree node. The RTC clock here is not a time-of-day clock, - but is instead a high-stability clock source for system timers - and cycle counters. -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock via the clock ID -macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. -These macros begin with PRCI_CLK_. - -The hfclk and rtcclk nodes are required, and represent physical -crystals or resonators located on the PCB. These nodes should be present -underneath /, rather than /soc. - -Examples: - -/* under /, in PCB-specific DT data */ -hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; -}; -rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - clock-output-names = "rtcclk"; -}; - -/* under /soc, in SoC-specific DT data */ -prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml new file mode 100644 index 0000000..49386cd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) + +maintainers: + - Sagar Kadam + - Paul Walmsley + +description: + On the FU540 family of SoCs, most system-wide clock and reset integration + is via the PRCI IP block. + The clock consumer should specify the desired clock via the clock ID + macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. + These macros begin with PRCI_CLK_. + + The hfclk and rtcclk nodes are required, and represent physical + crystals or resonators located on the PCB. These nodes should be present + underneath /, rather than /soc. + +properties: + compatible: + enum: + - sifive,fu540-c000-prci + description: + Should have "sifive,-prci", only one value is supported + + reg: + maxItems: 1 + description: Describe the PRCI's register target physical address region + + clocks: + description: + Should point to the hfclk device tree node and the rtcclk device tree node. + The RTC clock here is not a time-of-day clock, but is instead a high-stability + clock source for system timers and cycle counters. + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + //hfclk and rtcclk present under /, in PCB-specific DT data + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; + + //under /soc, in SoC-specific DT data + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x10000000 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + };