From patchwork Thu Oct 22 12:36:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11850993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7F21C388F9 for ; Thu, 22 Oct 2020 12:37:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6DE58223BF for ; Thu, 22 Oct 2020 12:37:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="h/su9oVk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2898284AbgJVMhv (ORCPT ); Thu, 22 Oct 2020 08:37:51 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:33534 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2898282AbgJVMhu (ORCPT ); Thu, 22 Oct 2020 08:37:50 -0400 X-UUID: b937429a00bf4012b55c58c03c66f5a2-20201022 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=NQbUYxMC/vO5/Luf2lSxEM/kUwLNngIueAFD5TmO+Kc=; b=h/su9oVkAcTy+byFd/oQUmDCWHQwn9blvaagcrE3/W3wfzfxf/nPXxD/DHAJmuBqM028sTiq9in60VgfWFmOeSOZzuedOaiBqU1wY/Xhih4wjEXcbem00JSGxp8pvAoW35FC3MS1cRvlLnWP1JG8VhGE/cc851cd1OBsa0piKKQ=; X-UUID: b937429a00bf4012b55c58c03c66f5a2-20201022 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 78721532; Thu, 22 Oct 2020 20:37:46 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Oct 2020 20:37:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Oct 2020 20:37:45 +0800 From: Weiyi Lu To: Matthias Brugger , Rob Herring , Stephen Boyd , Nicolas Boichat CC: , , , , , Weiyi Lu Subject: [PATCH v4 04/34] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller Date: Thu, 22 Oct 2020 20:36:57 +0800 Message-ID: <1603370247-30437-5-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1603370247-30437-1-git-send-email-weiyi.lu@mediatek.com> References: <1603370247-30437-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch adds the new binding documentation of msdc controller for Mediatek MT8192. Signed-off-by: Weiyi Lu --- .../bindings/arm/mediatek/mediatek,msdc.yaml | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml new file mode 100644 index 0000000..5aa9536 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,msdc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MSDC Controller + +maintainers: + - Weiyi Lu + +description: + The Mediatek msdc controller provides functional configurations and clocks to the system. + +properties: + compatible: + items: + - enum: + - mediatek,mt8192-msdc + - mediatek,mt8192-msdc_top + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +examples: + - | + msdc: syscon@11f60000 { + compatible = "mediatek,mt8192-msdc", "syscon"; + reg = <0 0x11f60000 0 0x1000>; + #clock-cells = <1>; + }; + + - | + msdc_top: syscon@11f10000 { + compatible = "mediatek,mt8192-msdc_top", "syscon"; + reg = <0 0x11f10000 0 0x1000>; + #clock-cells = <1>; + };