From patchwork Thu Oct 22 12:36:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11851045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EDB8C388F7 for ; Thu, 22 Oct 2020 12:43:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EE1624196 for ; Thu, 22 Oct 2020 12:43:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="EptQDCeT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2505992AbgJVMnL (ORCPT ); Thu, 22 Oct 2020 08:43:11 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:44187 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2505168AbgJVMnK (ORCPT ); Thu, 22 Oct 2020 08:43:10 -0400 X-UUID: a42a7ada98164c59b35a83be851ed7e3-20201022 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=vAXufp8oPq4yL34QGUZja+5laQrxJs+P3x47cbv2unU=; b=EptQDCeT3huBdgfT3MK+vm8UR1J8i5jVED7FPSxDmhEeDQ1GdcQiy2iUsbyvLUFv/7Ivt/iTZE3laGpWIpW29jXwyS/Ph7uJOl6zu83jx+zV69R9sD9Oulwjm5SEMvC3DV9pdGVL04z6KlkAV37IRgavO983S9qQqTzTTb48JzI=; X-UUID: a42a7ada98164c59b35a83be851ed7e3-20201022 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 76612940; Thu, 22 Oct 2020 20:37:53 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Oct 2020 20:37:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Oct 2020 20:37:51 +0800 From: Weiyi Lu To: Matthias Brugger , Rob Herring , Stephen Boyd , Nicolas Boichat CC: , , , , , Weiyi Lu Subject: [PATCH v4 06/34] dt-bindings: ARM: Mediatek: Add new document bindings of vdecsys soc controller Date: Thu, 22 Oct 2020 20:36:59 +0800 Message-ID: <1603370247-30437-7-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1603370247-30437-1-git-send-email-weiyi.lu@mediatek.com> References: <1603370247-30437-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch adds the new binding documentation of vdecsys soc controller for Mediatek MT8192. Signed-off-by: Weiyi Lu --- .../arm/mediatek/mediatek,vdecsys-soc.yaml | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml new file mode 100644 index 0000000..082f22e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,vdecsys-soc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek VDECSYS SOC Controller + +maintainers: + - Weiyi Lu + +description: + The Mediatek vdecsys soc controller provides functional configurations and clocks to the system. + +properties: + compatible: + items: + - enum: + - mediatek,mt8192-vdecsys_soc + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +examples: + - | + vdecsys_soc: syscon@1600f000 { + compatible = "mediatek,mt8192-vdecsys_soc", "syscon"; + reg = <0 0x1600f000 0 0x1000>; + #clock-cells = <1>; + };