From patchwork Mon Nov 9 02:03:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11890151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBDE9C4742C for ; Mon, 9 Nov 2020 02:04:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 679D120719 for ; Mon, 9 Nov 2020 02:04:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="eURTsWlj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728068AbgKICD7 (ORCPT ); Sun, 8 Nov 2020 21:03:59 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:57267 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728006AbgKICD7 (ORCPT ); Sun, 8 Nov 2020 21:03:59 -0500 X-UUID: 7dec71fd02864847bc6fd8c36d4da4a9-20201109 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=t6abyv7GQaCstliXITKrDOnJbXdw7pIR+rkQrfnHEvI=; b=eURTsWljrACT4cc0oIz2kutlB56jDOD8arqU3QIS/kgH4u5aIlRLl0bDB8o5zkNEjQQEdtUvm73YoOloLagIvZHiy6B2HZYfqqVDGDc7P8EtxbNLUv8Aed/bQ5XrtOldx+fBF2EGjcnwjxq+vadBsqURk6T8VMqI9Xgy5MSQJ48=; X-UUID: 7dec71fd02864847bc6fd8c36d4da4a9-20201109 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1082000444; Mon, 09 Nov 2020 10:03:53 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 9 Nov 2020 10:03:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 9 Nov 2020 10:03:52 +0800 From: Weiyi Lu To: Matthias Brugger , Rob Herring , Stephen Boyd , Nicolas Boichat CC: , , , , , Weiyi Lu , Yingjoe Chen Subject: [PATCH v5 09/24] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Date: Mon, 9 Nov 2020 10:03:34 +0800 Message-ID: <1604887429-29445-10-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com> References: <1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Most of subsystem clock providers only need to register clock gates in their probe() function. To reduce the duplicated code by add a generic function. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-mtk.c | 23 +++++++++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 8 ++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index cec1c8a..67693b7 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "clk-mtk.h" #include "clk-gate.h" @@ -286,3 +287,25 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, clk_data->clks[mcd->id] = clk; } } + +int mtk_clk_simple_probe(struct platform_device *pdev) +{ + const struct mtk_clk_desc *mcd; + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + mcd = of_device_get_match_data(&pdev->dev); + if (!mcd) + return -EINVAL; + + clk_data = mtk_alloc_clk_data(mcd->num_clks); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, clk_data); + if (r) + return r; + + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +} diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index c580663..2f61fba 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -10,6 +10,7 @@ #include #include #include +#include struct clk; struct clk_onecell_data; @@ -250,4 +251,11 @@ void mtk_register_reset_controller(struct device_node *np, void mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs); +struct mtk_clk_desc { + const struct mtk_gate *clks; + size_t num_clks; +}; + +int mtk_clk_simple_probe(struct platform_device *pdev); + #endif /* __DRV_CLK_MTK_H */