[v5,05/24] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers

Message ID	1604887429-29445-6-git-send-email-weiyi.lu@mediatek.com (mailing list archive)
State	Changes Requested, archived
Headers	show Return-Path: <SRS0=VQD0=EP=vger.kernel.org=linux-clk-owner@kernel.org> From: Weiyi Lu <weiyi.lu@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Nicolas Boichat <drinkcat@chromium.org> CC: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <srv_heupstream@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com>, Yingjoe Chen <yingjoe.chen@mediatek.com> Subject: [PATCH v5 05/24] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers Date: Mon, 9 Nov 2020 10:03:30 +0800 Message-ID: <1604887429-29445-6-git-send-email-weiyi.lu@mediatek.com> In-Reply-To: <1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com> References: <1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: base64 Precedence: bulk
Series	Mediatek MT8192 clock support \| expand [v5,00/24] Mediatek MT8192 clock support [v5,01/24] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller [v5,02/24] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller [v5,03/24] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller [v5,04/24] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller [v5,05/24] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers [v5,06/24] clk: mediatek: Add dt-bindings of MT8192 clocks [v5,07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control [v5,08/24] clk: mediatek: Add configurable enable control to mtk_pll_data [v5,09/24] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers [v5,10/24] clk: mediatek: Add MT8192 basic clocks support [v5,11/24] clk: mediatek: Add MT8192 audio clock support [v5,12/24] clk: mediatek: Add MT8192 camsys clock support [v5,13/24] clk: mediatek: Add MT8192 imgsys clock support [v5,14/24] clk: mediatek: Add MT8192 imp i2c wrapper clock support [v5,15/24] clk: mediatek: Add MT8192 ipesys clock support [v5,16/24] clk: mediatek: Add MT8192 mdpsys clock support [v5,17/24] clk: mediatek: Add MT8192 mfgcfg clock support [v5,18/24] clk: mediatek: Add MT8192 mmsys clock support [v5,19/24] clk: mediatek: Add MT8192 msdc clock support [v5,20/24] clk: mediatek: Add MT8192 scp adsp clock support [v5,21/24] clk: mediatek: Add MT8192 vdecsys clock support [v5,22/24] clk: mediatek: Add MT8192 vencsys clock support [v5,23/24] arm64: dts: mediatek: Add mt8192 clock controllers [v5,24/24] arm64: dts: mediatek: Correct UART0 bus clock of MT8192

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index ea827e87..551c307 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -18,6 +18,7 @@ Required Properties: - "mediatek,mt8167-apmixedsys", "syscon" - "mediatek,mt8173-apmixedsys" - "mediatek,mt8183-apmixedsys", "syscon" + - "mediatek,mt8192-apmixedsys", "syscon" - "mediatek,mt8516-apmixedsys" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index b32d374..699776b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -13,6 +13,7 @@ Required Properties: - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - "mediatek,mt8167-audiosys", "syscon" - "mediatek,mt8183-audiosys", "syscon" + - "mediatek,mt8192-audsys", "syscon" - "mediatek,mt8516-audsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt index a0ce820..7d0b14e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt @@ -9,6 +9,10 @@ Required Properties: - "mediatek,mt6765-camsys", "syscon" - "mediatek,mt6779-camsys", "syscon" - "mediatek,mt8183-camsys", "syscon" + - "mediatek,mt8192-camsys", "syscon" + - "mediatek,mt8192-camsys_rawa", "syscon" + - "mediatek,mt8192-camsys_rawb", "syscon" + - "mediatek,mt8192-camsys_rawc", "syscon" - #clock-cells: Must be 1 The camsys controller uses the common clk binding from @@ -22,3 +26,21 @@ camsys: camsys@1a000000 { reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + +camsys_rawa: syscon@1a04f000 { + compatible = "mediatek,mt8192-camsys_rawa", "syscon"; + reg = <0 0x1a04f000 0 0x1000>; + #clock-cells = <1>; +}; + +camsys_rawb: syscon@1a06f000 { + compatible = "mediatek,mt8192-camsys_rawb", "syscon"; + reg = <0 0x1a06f000 0 0x1000>; + #clock-cells = <1>; +}; + +camsys_rawc: syscon@1a08f000 { + compatible = "mediatek,mt8192-camsys_rawc", "syscon"; + reg = <0 0x1a08f000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt index dce4c924..b9e599e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt @@ -15,6 +15,8 @@ Required Properties: - "mediatek,mt8167-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon" - "mediatek,mt8183-imgsys", "syscon" + - "mediatek,mt8192-imgsys", "syscon" + - "mediatek,mt8192-imgsys2", "syscon" - #clock-cells: Must be 1 The imgsys controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index eb3523c..6e05a00 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -19,6 +19,7 @@ Required Properties: - "mediatek,mt8167-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - "mediatek,mt8183-infracfg", "syscon" + - "mediatek,mt8192-infracfg", "syscon" - "mediatek,mt8516-infracfg", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt index 2ce889b..9cd1035 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt6779-ipesys", "syscon" + - "mediatek,mt8192-ipesys", "syscon" - #clock-cells: Must be 1 The ipesys controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt index 054424f..6bfb49a 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt6779-mfgcfg", "syscon" - "mediatek,mt8167-mfgcfg", "syscon" - "mediatek,mt8183-mfgcfg", "syscon" + - "mediatek,mt8192-mfgcfg", "syscon" - #clock-cells: Must be 1 The mfgcfg controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index d8c9108..81fa345 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -15,6 +15,7 @@ Required Properties: - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon" - "mediatek,mt8183-mmsys", "syscon" + - "mediatek,mt8192-mmsys", "syscon" - #clock-cells: Must be 1 For the clock control, the mmsys controller uses the common clk binding from diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 8723dfe..b405cbc 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8135-pericfg - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg + - mediatek,mt8192-pericfg - mediatek,mt8516-pericfg - const: syscon - items: diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index 5ce7578..1627e38 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -18,6 +18,7 @@ Required Properties: - "mediatek,mt8167-topckgen", "syscon" - "mediatek,mt8173-topckgen" - "mediatek,mt8183-topckgen", "syscon" + - "mediatek,mt8192-topckgen", "syscon" - "mediatek,mt8516-topckgen" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt index 9819516..376c82e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt @@ -14,6 +14,8 @@ Required Properties: - "mediatek,mt8167-vdecsys", "syscon" - "mediatek,mt8173-vdecsys", "syscon" - "mediatek,mt8183-vdecsys", "syscon" + - "mediatek,mt8192-vdecsys", "syscon" + - "mediatek,mt8192-vdecsys_soc", "syscon" - #clock-cells: Must be 1 The vdecsys controller uses the common clk binding from @@ -27,3 +29,9 @@ vdecsys: clock-controller@16000000 { reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + +vdecsys_soc: syscon@1600f000 { + compatible = "mediatek,mt8192-vdecsys_soc", "syscon"; + reg = <0 0x1600f000 0 0x1000>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt index 6a6a14e..d22de01 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt @@ -11,6 +11,7 @@ Required Properties: - "mediatek,mt6797-vencsys", "syscon" - "mediatek,mt8173-vencsys", "syscon" - "mediatek,mt8183-vencsys", "syscon" + - "mediatek,mt8192-vencsys", "syscon" - #clock-cells: Must be 1 The vencsys controller uses the common clk binding from

[v5,05/24] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers

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