| Message ID | 1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | clk: at91: clk-master: re-factor master clock | expand |
Quoting Claudiu Beznea (2020-11-19 07:43:14) > On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and > CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is > also changed by DVFS to avoid over/under clocking of MCK0 consumers. > The lower limit is changed to be able to set MCK0 accordingly by > DVFS. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 335e9c943c65..29d9781e6712 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -807,7 +807,7 @@ static const struct clk_pll_characteristics pll_characteristics = { /* MCK0 characteristics. */ static const struct clk_master_characteristics mck0_characteristics = { - .output = { .min = 140000000, .max = 200000000 }, + .output = { .min = 50000000, .max = 200000000 }, .divisors = { 1, 2, 4, 3, 5 }, .have_div3_pres = 1, };
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is also changed by DVFS to avoid over/under clocking of MCK0 consumers. The lower limit is changed to be able to set MCK0 accordingly by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- drivers/clk/at91/sama7g5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)