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Wed, 2 Dec 2020 05:41:39 +0000 From: Liu Ying To: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, robh+dt@kernel.org, aisheng.dong@nxp.com Subject: [PATCH v2 4/4] clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems Date: Wed, 2 Dec 2020 13:33:39 +0800 Message-Id: <1606887219-5854-5-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606887219-5854-1-git-send-email-victor.liu@nxp.com> References: <1606887219-5854-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0091.apcprd03.prod.outlook.com (2603:1096:4:7c::19) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR03CA0091.apcprd03.prod.outlook.com (2603:1096:4:7c::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3632.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Tsv3y+J2Nay1wfc4roIn5ZhgFJGK4MMthqlMQJm8v73MQOUG2HEuJrk1cf83VQXeiad7/k3DJr3oi9dUyhHDTCcdgqKDk8CvpCMe98BpYJsSD80PxnE4kp8ctTUBznAl2MonzVMTQS+oQNo5YfiIYi0OkXdFqN66tTAbx1x+COwxaeOFUU5xBy9m0uOHcKGOnVFd8h+1hYKenKRhI2B78sKLGIY3YFgZHfN8TGw1n+PxaMH4vFqCpQcw3gUiYc6b11cmSwLcy7UT6HwB2V51Vk3SfRVf+7EapM0LAvZaCB3Qh49ajnFQ/zubsKzE512i2xg4j5Ct3cAbTLCTTsMV9hKASWAJl1a2bQmYMt6Vd8ue3v/pIdzsQHEPL1/hVKQs9S8sZn6uN5NlwCgINXydc2AujxaSQ/wDp480n7BWSulLG9SjemDnvF/4GEItxN8c2eDg91LtMn0ndYGvPM8/1WzpfITCEVQBJ/Ea7K7KgfN0mXkATwMocv431hsW2VCHdsOKgjsDsPA7XNTgBIjBG2g2LeFNyz9T/5q2Bm+BSCaUJey9PvwAPSi+ftgAA2jVF0h9vfTbLJp34kKgi9OG31vT39HNPeGroU9vuvcwq3lVOSwGt4hA/HS1lN1irh8oTOjrFiwCvjMCcFyfDer/ApQNY9h35h8Tm4yl1NROR4bCP6EIpavl/XOQj/b5B1uNMAMzUHzlF78EteNkakEhmvSnVm2OATojUFKr4lntqJoDIYRcn7mUT69sXu17j5Qred0few+En0FnDqoGPbyZwO/khAExxjT1zpRoUCya79ekMI+SwM9wn8tAk/0VWbiwbB9C17vrZwSOPkmWkjQNKfNdg/nuyAqXh8PsAHaBdZ6GEDcDcPbfWQb3UvyUaUAMWpHtiLW/noswWibftQK35VgEAAW5pdbU3aqPSa47pSSxxZtTqKvH0mRVHM4JH+FUH0WxDxTm1lGfm4DFMEYiW95obDF5xD6F6+VsH6f8epVq/L0E3bjeBEe27iPjo5wp X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55f07647-95d0-4a8e-aaf5-08d89684f0a5 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2020 05:41:39.3621 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lKae0BbUxjYmGOdwY47HwuEJvME7roQJl12Vb+36bXQppZARpFeBNMVI0n8ujUXKjM+1Qm+HvJfctPrPxq2LLQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7085 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch adds some SCU clocks support for i.MX8qxp MIPI-LVDS subsystems. Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Dong Aisheng Signed-off-by: Liu Ying --- v1->v2: * No change. drivers/clk/imx/clk-imx8qxp.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 0b4bb2c..fbf1170 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -131,8 +131,18 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) clks[IMX_DC0_BYPASS1_CLK] = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells); /* MIPI-LVDS SS */ + clks[IMX_MIPI0_LVDS_PIXEL_CLK] = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells); + clks[IMX_MIPI0_LVDS_PHY_CLK] = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells); clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells); clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI0_PWM0_CLK] = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); + clks[IMX_MIPI1_LVDS_PIXEL_CLK] = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells); + clks[IMX_MIPI1_LVDS_PHY_CLK] = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells); + clks[IMX_MIPI1_I2C0_CLK] = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI1_I2C1_CLK] = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells); + clks[IMX_MIPI1_PWM0_CLK] = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells); /* MIPI CSI SS */ clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);