| Message ID | 1608644414-17793-3-git-send-email-weiyi.lu@mediatek.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add MediaTek MT8192 clock provider device nodes | expand |
On 22/12/2020 14:40, Weiyi Lu wrote: > infra_uart0 clock is the real one what uart0 uses as bus clock. > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 92dcfbd..ac5dca6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -283,7 +283,7 @@ > "mediatek,mt6577-uart"; > reg = <0 0x11002000 0 0x1000>; > interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; > - clocks = <&clk26m>, <&clk26m>; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; Please update the clocks for all nodes to use the clock driver, not just uart or uart0. Thanks, Matthias > clock-names = "baud", "bus"; > status = "disabled"; > }; >
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 92dcfbd..ac5dca6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -283,7 +283,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; status = "disabled"; };
infra_uart0 clock is the real one what uart0 uses as bus clock. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)