From patchwork Thu Apr 15 05:52:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Fu X-Patchwork-Id: 12204497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95E54C433ED for ; Thu, 15 Apr 2021 05:52:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 73A0B61421 for ; Thu, 15 Apr 2021 05:52:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230426AbhDOFxU (ORCPT ); Thu, 15 Apr 2021 01:53:20 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48116 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230384AbhDOFxS (ORCPT ); Thu, 15 Apr 2021 01:53:18 -0400 X-UUID: c783005b5ec24466a25de45071b422bc-20210415 X-UUID: c783005b5ec24466a25de45071b422bc-20210415 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 867824182; Thu, 15 Apr 2021 13:52:53 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 15 Apr 2021 13:52:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 15 Apr 2021 13:52:50 +0800 From: Flora Fu To: Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd CC: Liam Girdwood , Mark Brown , Flora Fu , Pi-Cheng Chen , Chiawen Lee , Chun-Jie Chen , , , , , , Subject: [PATCH v2 3/7] dt-bindings: arm: mediatek: Add new document bindings for APU Date: Thu, 15 Apr 2021 13:52:36 +0800 Message-ID: <1618465960-3013-4-git-send-email-flora.fu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1618465960-3013-1-git-send-email-flora.fu@mediatek.com> References: <1618465960-3013-1-git-send-email-flora.fu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 16CE3117B475B4EDD03E74C2F10B07A397CF72A65CC12EBB254D20C05A6BDD232000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Document the apusys bindings. Signed-off-by: Flora Fu --- .../arm/mediatek/mediatek,apusys.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml new file mode 100644 index 000000000000..d46290548b34 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,apusys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek APUSYS Controller + +maintainers: + - Flora Fu + +description: + The Mediatek apusys controller provides functional configurations and clocks + to the system. + +properties: + compatible: + items: + - enum: + - mediatek,mt8192-apu-mbox + - mediatek,mt8192-apu-conn + - mediatek,mt8192-apu-vcore + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + apu_mbox: apu_mbox@19000000 { + compatible = "mediatek,mt8192-apu-mbox", "syscon"; + reg = <0x19000000 0x1000>; + }; + + - | + apu_conn: apu_conn@19020000 { + compatible = "mediatek,mt8192-apu-conn", "syscon"; + reg = <0x19020000 0x1000>; + #clock-cells = <1>; + }; + + - | + apu_vcore: apu_vcore@19029000 { + compatible = "mediatek,mt8192-apu-vcore", "syscon"; + reg = <0x19029000 0x1000>; + #clock-cells = <1>; + };