From patchwork Thu Apr 15 05:52:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Flora Fu X-Patchwork-Id: 12204501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3333C43462 for ; Thu, 15 Apr 2021 05:53:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 865B461429 for ; Thu, 15 Apr 2021 05:53:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230415AbhDOFxY (ORCPT ); Thu, 15 Apr 2021 01:53:24 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48167 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230400AbhDOFxV (ORCPT ); Thu, 15 Apr 2021 01:53:21 -0400 X-UUID: 491c0a29e5ac42648ce6c520b93ffde2-20210415 X-UUID: 491c0a29e5ac42648ce6c520b93ffde2-20210415 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 239175052; Thu, 15 Apr 2021 13:52:55 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 15 Apr 2021 13:52:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 15 Apr 2021 13:52:53 +0800 From: Flora Fu To: Rob Herring , Matthias Brugger , Michael Turquette , Stephen Boyd CC: Liam Girdwood , Mark Brown , Flora Fu , Pi-Cheng Chen , Chiawen Lee , Chun-Jie Chen , , , , , , Subject: [PATCH v2 6/7] arm64: dts: mt8192: Add APU node Date: Thu, 15 Apr 2021 13:52:39 +0800 Message-ID: <1618465960-3013-7-git-send-email-flora.fu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1618465960-3013-1-git-send-email-flora.fu@mediatek.com> References: <1618465960-3013-1-git-send-email-flora.fu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add APU node to MT8192. Signed-off-by: Flora Fu --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index eb17274c3719..561025d2ebab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1016,6 +1016,23 @@ #clock-cells = <1>; }; + apu_mbox: apu_mbox@19000000 { + compatible = "mediatek,mt8192-apu-mbox", "syscon"; + reg = <0 0x19000000 0 0x1000>; + }; + + apu_conn: apu_conn@19020000 { + compatible = "mediatek,mt8192-apu-conn", "syscon"; + reg = <0 0x19020000 0 0x1000>; + #clock-cells = <1>; + }; + + apu_vcore: apu_vcore@19029000 { + compatible = "mediatek,mt8192-apu-vcore", "syscon"; + reg = <0 0x19029000 0 0x1000>; + #clock-cells = <1>; + }; + larb13: larb@1a001000 { compatible = "mediatek,mt8192-smi-larb"; reg = <0 0x1a001000 0 0x1000>;