diff mbox series

[v3,1/5] clk: uniphier: Add audio system and video input clock control for PXs3

Message ID 1634000035-3114-2-git-send-email-hayashi.kunihiko@socionext.com (mailing list archive)
State Accepted, archived
Headers show
Series clk: uniphier: Introduce some clock features and NX1 support | expand

Commit Message

Kunihiko Hayashi Oct. 12, 2021, 12:53 a.m. UTC
Add clocks for audio subsystem (AIO) and video input subsystem (EXIV) on
UniPhier PXs3 SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/clk/uniphier/clk-uniphier-sys.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Stephen Boyd Nov. 2, 2021, 9:37 p.m. UTC | #1
Quoting Kunihiko Hayashi (2021-10-11 17:53:51)
> Add clocks for audio subsystem (AIO) and video input subsystem (EXIV) on
> UniPhier PXs3 SoC.
> 
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---

Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 32b301724183..0ec28ebc39c2 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -288,6 +288,8 @@  const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
 	UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
 	UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
+	UNIPHIER_LD11_SYS_CLK_AIO(40),
+	UNIPHIER_LD11_SYS_CLK_EXIV(42),
 	/* CPU gears */
 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 	UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),