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[RESEND,v3,2/4] dt-bindings: clock: qcom,sc7280-lpasscc: Add resets for audioreach

Message ID 1672847892-25154-3-git-send-email-quic_srivasam@quicinc.com (mailing list archive)
State Superseded, archived
Headers show
Series Add resets for ADSP based audio clock controller driver | expand

Commit Message

Srinivasa Rao Mandadapu Jan. 4, 2023, 3:58 p.m. UTC 
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for audioreach based SC7280 platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 .../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml       | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 97c6bd9..054c496 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -31,15 +31,20 @@  properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    const: 1
+
   reg:
     items:
       - description: LPASS qdsp6ss register
       - description: LPASS top-cc register
+      - description: LPASS reset-cgcr register
 
   reg-names:
     items:
       - const: qdsp6ss
       - const: top_cc
+      - const: reset_cgcr
 
   qcom,adsp-pil-mode:
     description:
@@ -62,11 +67,14 @@  examples:
     #include <dt-bindings/clock/qcom,lpass-sc7280.h>
     clock-controller@3000000 {
       compatible = "qcom,sc7280-lpasscc";
-      reg = <0x03000000 0x40>, <0x03c04000 0x4>;
-      reg-names = "qdsp6ss", "top_cc";
+      reg = <0x03000000 0x40>,
+            <0x03c04000 0x4>,
+            <0x032a9000 0x1000>;
+      reg-names = "qdsp6ss", "top_cc", "reset_cgcr";
       clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
       clock-names = "iface";
       qcom,adsp-pil-mode;
       #clock-cells = <1>;
+      #reset-cells = <1>;
     };
 ...