diff mbox series

clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks

Message ID 1693377310-8540-1-git-send-email-quic_varada@quicinc.com (mailing list archive)
State Changes Requested, archived
Headers show
Series clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks | expand

Commit Message

Varadarajan Narayanan Aug. 30, 2023, 6:35 a.m. UTC
IPQ5332's GPLL0's nominal/turbo frequency is 800MHz.
This must not be scaled based on the requirement of
dependent clocks. Hence remove the CLK_SET_RATE_PARENT
flag.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq5332.c | 2 --
 1 file changed, 2 deletions(-)

Comments

Stephen Boyd Aug. 30, 2023, 11:37 p.m. UTC | #1
Quoting Varadarajan Narayanan (2023-08-29 23:35:10)
> IPQ5332's GPLL0's nominal/turbo frequency is 800MHz.
> This must not be scaled based on the requirement of
> dependent clocks. Hence remove the CLK_SET_RATE_PARENT
> flag.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---

Any Fixes tag?
Varadarajan Narayanan Aug. 31, 2023, 9:30 a.m. UTC | #2
On Wed, Aug 30, 2023 at 04:37:40PM -0700, Stephen Boyd wrote:
> Quoting Varadarajan Narayanan (2023-08-29 23:35:10)
> > IPQ5332's GPLL0's nominal/turbo frequency is 800MHz.
> > This must not be scaled based on the requirement of
> > dependent clocks. Hence remove the CLK_SET_RATE_PARENT
> > flag.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
>
> Any Fixes tag?

Have posted v2 with Fixes tag. Please take a look.

Thanks
Varada
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index b02026f..b836159 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -71,7 +71,6 @@  static struct clk_fixed_factor gpll0_div2 = {
 				&gpll0_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -85,7 +84,6 @@  static struct clk_alpha_pll_postdiv gpll0 = {
 				&gpll0_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };