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[v3,6/6] arm64: dts: imx8mp: Add reset-controller sub node for audio_blk_ctrl

Message ID 1715679210-9588-7-git-send-email-shengjiu.wang@nxp.com (mailing list archive)
State Not Applicable, archived
Headers show
Series clk: imx: clk-audiomix: Improvement for audiomix | expand

Commit Message

Shengjiu Wang May 14, 2024, 9:33 a.m. UTC 
The Audio Block Control contains clock distribution and gating
controls, as well as reset handling to several of the AUDIOMIX
peripherals. Especially the reset controls for Enhanced Audio
Return Channel (EARC) PHY and Controller

Add reset-controller sub-node for audio_blk_ctrl.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 459c4a54d30e..f94702ad4210 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1565,7 +1565,7 @@  sdma2: dma-controller@30e10000 {
 			};
 
 			audio_blk_ctrl: clock-controller@30e20000 {
-				compatible = "fsl,imx8mp-audio-blk-ctrl";
+				compatible = "fsl,imx8mp-audio-blk-ctrl", "syscon", "simple-mfd";
 				reg = <0x30e20000 0x10000>;
 				#clock-cells = <1>;
 				clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
@@ -1582,6 +1582,11 @@  audio_blk_ctrl: clock-controller@30e20000 {
 				assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
 						  <&clk IMX8MP_AUDIO_PLL2>;
 				assigned-clock-rates = <393216000>, <361267200>;
+
+				audio_blk_ctrl_rst: reset-controller {
+					compatible = "fsl,imx8mp-audiomix-reset";
+					#reset-cells = <1>;
+				};
 			};
 		};