| Message ID | 1cbbf50917ef9d2e2bc2c8862cb8425d54959049.1657276107.git.shubhrajyoti.datta@xilinx.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [LINUX] dt-bindings: clock: versal: Remove alt_ref_clk from clock source | expand |
On Fri, 08 Jul 2022 16:11:12 +0530, Shubhrajyoti Datta wrote: > alt_ref_clk is applicable only for PS extended version. > For PS base version there is no separate alt_ref_clk. > It is tied with ref_clk. The commit > 2b2012d1c1d8 (clk: versal: Remove alt_ref_clk from clock sources) > removes the alt_ref_clk from the u-boot code but not the yaml. > Remove it from yaml as well. > > Fixes: 026049cf37f2 ("clk: versal: Remove alt_ref_clk from clock sources") > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > u-boot commit refered > https://source.denx.de/u-boot/u-boot/-/commit/2b2012d1c1d8515417ba139339d0aa9b47789dca > > .../devicetree/bindings/clock/xlnx,versal-clk.yaml | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.example.dtb: versal-firmware: clock-controller:clocks: [[4294967295], [4294967295], [4294967295]] is too long From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.example.dtb: versal-firmware: clock-controller:clock-names:1: 'pl_alt_ref' was expected From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.example.dtb: versal-firmware: clock-controller:clock-names: ['ref', 'alt_ref', 'pl_alt_ref'] is too long From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 229af98b1d30..59aaaffbdc9b 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -30,13 +30,11 @@ properties: clocks to the given clock controller. items: - description: reference clock - - description: alternate reference clock - description: alternate reference clock for programmable logic clock-names: items: - const: ref - - const: alt_ref - const: pl_alt_ref required: @@ -56,8 +54,8 @@ examples: versal_clk: clock-controller { #clock-cells = <1>; compatible = "xlnx,versal-clk"; - clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>; - clock-names = "ref", "alt_ref", "pl_alt_ref"; + clocks = <&ref>, <&pl_alt_ref>; + clock-names = "ref", "pl_alt_ref"; }; }; };
alt_ref_clk is applicable only for PS extended version. For PS base version there is no separate alt_ref_clk. It is tied with ref_clk. The commit 2b2012d1c1d8 (clk: versal: Remove alt_ref_clk from clock sources) removes the alt_ref_clk from the u-boot code but not the yaml. Remove it from yaml as well. Fixes: 026049cf37f2 ("clk: versal: Remove alt_ref_clk from clock sources") Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- u-boot commit refered https://source.denx.de/u-boot/u-boot/-/commit/2b2012d1c1d8515417ba139339d0aa9b47789dca .../devicetree/bindings/clock/xlnx,versal-clk.yaml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)