From patchwork Tue Jun 7 21:56:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roman Volkov X-Patchwork-Id: 9162689 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0D69660467 for ; Tue, 7 Jun 2016 22:02:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F195B2835C for ; Tue, 7 Jun 2016 22:02:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E63962836C; Tue, 7 Jun 2016 22:02:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, FREEMAIL_FROM,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A56A42835C for ; Tue, 7 Jun 2016 22:02:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933524AbcFGWB4 (ORCPT ); Tue, 7 Jun 2016 18:01:56 -0400 Received: from fallback4.mail.ru ([94.100.181.169]:55534 "EHLO fallback4.mail.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932652AbcFGWBy (ORCPT ); Tue, 7 Jun 2016 18:01:54 -0400 Received: from smtp49.i.mail.ru (smtp49.i.mail.ru [94.100.177.109]) by fallback4.mail.ru (mPOP.Fallback_MX) with ESMTP id 8D6E01D694CE; Wed, 8 Jun 2016 01:01:50 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=TJHINHDr+6Onn2Ax1TNLNpwDyzDk1XQGZBETXg4/AQg=; b=uPSnPslzCKdEvnTdaKiWSZbK9a9uQSwzoKk66iie1uTEX4IDr1i0l+wZNFqNcFxdAhR0HwqziUPyEDxSf8JWm+7jjyd5BkQGdr3z+j7c3KMmjJR08SCJ10ZWPhTIIFBy2RcDpMZTi2rC+olLY688S8FlQhzmThgKVmTl6eOaoFU=; Received: from [176.213.0.46] (port=59720 helo=v1ron-s7.localdomain) by smtp49.i.mail.ru with esmtpa (envelope-from ) id 1bAP47-0007MP-VR; Wed, 08 Jun 2016 01:01:40 +0300 From: Roman Volkov To: Stephen Boyd Cc: Arnd Bergmann , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Turquette , Roman Volkov , Tony Prisk Subject: [PATCH v2 2/2] clk: vt8500: rework wm8650_find_pll_bits() Date: Wed, 8 Jun 2016 00:56:10 +0300 Message-Id: <20160607215610.8724-3-v1ron@mail.ru> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160607215610.8724-1-v1ron@mail.ru> References: <20160607215610.8724-1-v1ron@mail.ru> X-Mras: OK Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Roman Volkov PLL clock on WM8650 is calculated in the following way: M * parent [O1] => / P [O2] => / D [O3] Where O2 is 600MHz >= (M * parent) / P >= 300MHz. Current algorithm does not met this requirement, so that the function may return rates which are not supported by the hardware. This patch fixes the algorithm and simplifies the code, reducing the calculation time by ~10000 times (according to usermode app) by removing the nested loops. Signed-off-by: Roman Volkov --- drivers/clk/clk-vt8500.c | 73 +++++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 35 deletions(-) diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index d5a3453970d0..37368a399ff9 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -383,47 +383,50 @@ static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, return 0; } -static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate, - u32 *multiplier, u32 *divisor1, u32 *divisor2) +/* + * M * parent [O1] => / P [O2] => / D [O3] + * Where O1 is 900MHz...3GHz; + * O2 is 600MHz >= (M * parent) / P >= 300MHz; + * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8. + * Possible ranges (O3): + * D = 8: 37,5MHz...75MHz + * D = 4: 75MHz...150MHz + * D = 2: 150MHz...300MHz + * D = 1: 300MHz...600MHz + */ +static int wm8650_find_pll_bits(unsigned long rate, + unsigned long parent_rate, u32 *multiplier, u32 *divisor1, + u32 *divisor2) { - u32 mul, div1; - int div2; - unsigned long tclk, rate_err, best_err; - - best_err = (unsigned long)-1; + unsigned long O1, min_err, rate_err; - /* Find the closest match (lower or equal to requested) */ - for (div1 = 5; div1 >= 3; div1--) - for (div2 = 3; div2 >= 0; div2--) - for (mul = 3; mul <= 1023; mul++) { - tclk = parent_rate * mul / (div1 * (1 << div2)); - if (tclk > rate) - continue; - /* error will always be +ve */ - rate_err = rate - tclk; - if (rate_err == 0) { - *multiplier = mul; - *divisor1 = div1; - *divisor2 = div2; - return 0; - } + if (!parent_rate || (rate < 37500000) || (rate > 600000000)) + return -EINVAL; - if (rate_err < best_err) { - best_err = rate_err; - *multiplier = mul; - *divisor1 = div1; - *divisor2 = div2; - } - } + *divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 : + rate <= 300000000 ? 1 : 0; + /* + * Divisor P cannot be calculated. Test all divisors and find where M + * will be as close as possible to the requested rate. + */ + min_err = ULONG_MAX; + for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) { + O1 = rate * *divisor1 * (1 << (*divisor2)); + rate_err = O1 % parent_rate; + if (rate_err < min_err) { + *multiplier = O1 / parent_rate; + if (rate_err == 0) + return 0; + + min_err = rate_err; + } + } - if (best_err == (unsigned long)-1) { - pr_warn("%s: impossible rate %lu\n", __func__, rate); + if ((*multiplier < 3) || (*multiplier > 1023)) return -EINVAL; - } - /* if we got here, it wasn't an exact match */ - pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, - rate - best_err); + pr_warn("%s: rate error is %lu\n", __func__, min_err); + return 0; }