| Message ID | 20160621153035.22172-1-thierry.reding@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On 6/21/2016 11:30 AM, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The timer clock feeds the timer block, which, among other things, is > used to drive the SOR lane sequencer. Since the Tegra timer driver is > not enabled on 64-bit ARM, nothing currently claims that clock and it > gets disabled by the common clock framework at late_init time. > > Given the non-obvious dependencies, the timer clock can be considered > a critical part of the SoC infrastructure, requiring its clock source > to be always on. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > index af85c8aeaf5a..4ce4e7fb1124 100644 > --- a/drivers/clk/tegra/clk-tegra-periph.c > +++ b/drivers/clk/tegra/clk-tegra-periph.c > @@ -792,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = { > > static struct tegra_periph_init_data gate_clks[] = { > GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), > - GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), > + GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), > GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), > GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), > GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), > Acked-by: Rhyland Klein <rklein@nvidia.com>
On Tue, Jun 21, 2016 at 05:30:35PM +0200, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > The timer clock feeds the timer block, which, among other things, is > used to drive the SOR lane sequencer. Since the Tegra timer driver is > not enabled on 64-bit ARM, nothing currently claims that clock and it > gets disabled by the common clock framework at late_init time. > > Given the non-obvious dependencies, the timer clock can be considered > a critical part of the SoC infrastructure, requiring its clock source > to be always on. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk-tegra-periph.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c > index af85c8aeaf5a..4ce4e7fb1124 100644 > --- a/drivers/clk/tegra/clk-tegra-periph.c > +++ b/drivers/clk/tegra/clk-tegra-periph.c > @@ -792,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = { > > static struct tegra_periph_init_data gate_clks[] = { > GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), > - GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), > + GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), > GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), > GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), > GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index af85c8aeaf5a..4ce4e7fb1124 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -792,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = { static struct tegra_periph_init_data gate_clks[] = { GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), - GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), + GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),