From patchwork Wed Jun 22 09:15:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 9192237 X-Patchwork-Delegate: sboyd@codeaurora.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A4DC56075C for ; Wed, 22 Jun 2016 09:24:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92F3827F85 for ; Wed, 22 Jun 2016 09:24:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 85C63283EC; Wed, 22 Jun 2016 09:24:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF20F283A6 for ; Wed, 22 Jun 2016 09:24:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751216AbcFVJYf (ORCPT ); Wed, 22 Jun 2016 05:24:35 -0400 Received: from down.free-electrons.com ([37.187.137.238]:58828 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751394AbcFVJYd (ORCPT ); Wed, 22 Jun 2016 05:24:33 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id EB81C21C; Wed, 22 Jun 2016 11:16:06 +0200 (CEST) Received: from localhost (164.121.153.77.rev.sfr.net [77.153.121.164]) by mail.free-electrons.com (Postfix) with ESMTPSA id A55AC51; Wed, 22 Jun 2016 11:15:56 +0200 (CEST) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , Jongsung Kim Cc: Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Maxime Ripard Subject: [PATCH 1/2] clk: fixed-factor: Allow for a few clocks to change the parent rate Date: Wed, 22 Jun 2016 11:15:54 +0200 Message-Id: <20160622091555.18415-1-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.9.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The only way for a fixed factor clock to change its rate would be to change its parent rate. Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms that were relying on the fact that the parent rate wouldn't change, introduce a compatible-based whitelist that will allow clocks to opt-in that flag. Signed-off-by: Maxime Ripard Acked-by: Rob Herring --- .../devicetree/bindings/clock/fixed-factor-clock.txt | 4 ++++ drivers/clk/clk-fixed-factor.c | 11 ++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt index 1bae8527eb9b..189467a7188a 100644 --- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt +++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt @@ -14,6 +14,10 @@ Required properties: Optional properties: - clock-output-names : From common clock binding. +Some clocks that require special treatments are also handled by that +driver, with the compatibles: + - allwinner,sun4i-a10-pll3-2x-clk + Example: clock { compatible = "fixed-factor-clock"; diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 75cd6c792cb8..4db3be214077 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -142,6 +142,11 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw) EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor); #ifdef CONFIG_OF +static const struct of_device_id set_rate_parent_matches[] = { + { .compatible = "allwinner,sun4i-a10-pll3-2x-clk" }, + { /* Sentinel */ }, +}; + /** * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock */ @@ -150,6 +155,7 @@ void __init of_fixed_factor_clk_setup(struct device_node *node) struct clk *clk; const char *clk_name = node->name; const char *parent_name; + unsigned long flags = 0; u32 div, mult; if (of_property_read_u32(node, "clock-div", &div)) { @@ -167,7 +173,10 @@ void __init of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); parent_name = of_clk_get_parent_name(node, 0); - clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, + if (of_match_node(set_rate_parent_matches, node)) + flags |= CLK_SET_RATE_PARENT; + + clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags, mult, div); if (!IS_ERR(clk)) of_clk_add_provider(node, of_clk_src_simple_get, clk);