From patchwork Wed Jun 22 09:15:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 9192239 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2E8A06075C for ; Wed, 22 Jun 2016 09:24:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D99E27D13 for ; Wed, 22 Jun 2016 09:24:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 128FD283A6; Wed, 22 Jun 2016 09:24:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0C47A27D13 for ; Wed, 22 Jun 2016 09:24:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751394AbcFVJYg (ORCPT ); Wed, 22 Jun 2016 05:24:36 -0400 Received: from down.free-electrons.com ([37.187.137.238]:58829 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751446AbcFVJYd (ORCPT ); Wed, 22 Jun 2016 05:24:33 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id D2716166; Wed, 22 Jun 2016 11:16:07 +0200 (CEST) Received: from localhost (164.121.153.77.rev.sfr.net [77.153.121.164]) by mail.free-electrons.com (Postfix) with ESMTPSA id 91DF7141; Wed, 22 Jun 2016 11:15:57 +0200 (CEST) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , Jongsung Kim Cc: Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Maxime Ripard Subject: [PATCH 2/2] ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate Date: Wed, 22 Jun 2016 11:15:55 +0200 Message-Id: <20160622091555.18415-2-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160622091555.18415-1-maxime.ripard@free-electrons.com> References: <20160622091555.18415-1-maxime.ripard@free-electrons.com> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to be able to properly generate its pixel clock, the pll3-2x fixed factor needs to be able to change the PLL3 rate too. Add the needed extra compatible so that it behaves that way. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 0840612b5ed6..e374f4fc8073 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -130,7 +130,7 @@ }; pll3x2: pll3x2_clk { - compatible = "fixed-factor-clock"; + compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; clock-mult = <2>;