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Tue, 28 Jun 2016 05:33:32 +0000 From: Bhuvanchandra DV To: CC: , , , , , , , , , , Bhuvanchandra DV Subject: [PATCH v2 8/9] tty: serial: fsl-lpuart: Update suspend/resume for DMA mode Date: Tue, 28 Jun 2016 11:02:34 +0530 Message-ID: <20160628053235.5114-9-bhuvanchandra.dv@toradex.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160628053235.5114-1-bhuvanchandra.dv@toradex.com> References: <20160628053235.5114-1-bhuvanchandra.dv@toradex.com> MIME-Version: 1.0 X-Originating-IP: [115.115.243.34] X-ClientProxiedBy: BM1PR01CA0056.INDPRD01.PROD.OUTLOOK.COM (10.163.199.28) To HE1PR0501MB2089.eurprd05.prod.outlook.com (10.167.246.9) X-MS-Office365-Filtering-Correlation-Id: a63eb9ed-a75e-4092-21bb-08d39f15bff7 X-Microsoft-Exchange-Diagnostics: 1; HE1PR0501MB2089; 2:SSRGaOVCyh2PdfVq3Q24UgvuSJvKVKUNWbRvb7F4ojEftow3Mi/bUOLi/PLn0KmRtig/TkcHARaryLirUAbMqOu3S261LJuSO1dm8Gn+rtuuBExO0Gqxrifx2Hu2oPRBTahmC6iUwD0SKxA8NVaEtiE+JzqLNWXBy3C/6ris4vkGeG8kqjfRi3Tij4CvsTUQ; 3:rYK9BjJdClnCp/WxZBFarS222cjFRYXNpcUUkoGx1jN3+3XjUft+a4oBwfLHed/MuWMlgs98RFvquJYmJH0aJ6QIVirbC2pYe7g9h6VLT1UxjW1YL2XopRjDYO6OVvME; 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This patch takes care of gracefully releasing DMA channels for the above two cases and start the DMA at resume. Signed-off-by: Bhuvanchandra DV --- drivers/tty/serial/fsl_lpuart.c | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 27687d5..134090a 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -1943,6 +1943,30 @@ static int lpuart_suspend(struct device *dev) } uart_suspend_port(&lpuart_reg, &sport->port); + + if (sport->lpuart_dma_rx_use) { + /* + * EDMA driver during suspend will forcefully release any + * non-idle DMA channels. If port wakeup is enabled or if port + * is console port or 'no_console_suspend' is set the Rx DMA + * cannot resume as as expected, hence gracefully release the + * Rx DMA path before suspend and start Rx DMA path on resume. + */ + if (sport->port.irq_wake) { + del_timer_sync(&sport->lpuart_timer); + lpuart_dma_rx_free(&sport->port); + } + + /* Disable Rx DMA to use UART port as wakeup source */ + writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, + sport->port.membase + UARTCR5); + } + + if (sport->lpuart_dma_tx_use) { + sport->dma_tx_in_progress = false; + dmaengine_terminate_all(sport->dma_tx_chan); + } + if (sport->port.suspended && !sport->port.irq_wake) clk_disable_unprepare(sport->clk); @@ -1970,6 +1994,26 @@ static int lpuart_resume(struct device *dev) writeb(temp, sport->port.membase + UARTCR2); } + if (sport->lpuart_dma_rx_use) { + if (sport->port.irq_wake) { + if (!lpuart_start_rx_dma(sport)) { + sport->lpuart_dma_rx_use = true; + rx_dma_timer_init(sport); + } else { + sport->lpuart_dma_rx_use = false; + } + } + } + + if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { + init_waitqueue_head(&sport->dma_wait); + sport->lpuart_dma_tx_use = true; + writeb(readb(sport->port.membase + UARTCR5) | + UARTCR5_TDMAS, sport->port.membase + UARTCR5); + } else { + sport->lpuart_dma_tx_use = false; + } + uart_resume_port(&lpuart_reg, &sport->port); return 0;